CMOS Logic Circuit Design:
CMOS Logic Circuit Design is an up-to-date treatment of the analysis and design of CMOS integrated digital logic circuits. It is a self- contained treatment that covers all of the important digital circuit design styles found in modern CMOS chips. Introductory chapters on MOSFET physics and CMOS fab...
Gespeichert in:
1. Verfasser: | |
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Format: | Elektronisch E-Book |
Sprache: | English |
Veröffentlicht: |
Boston, MA
Springer US
2001
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Schlagworte: | |
Online-Zugang: | FHI01 BTU01 Volltext |
Zusammenfassung: | CMOS Logic Circuit Design is an up-to-date treatment of the analysis and design of CMOS integrated digital logic circuits. It is a self- contained treatment that covers all of the important digital circuit design styles found in modern CMOS chips. Introductory chapters on MOSFET physics and CMOS fabrication provide the background needed for a solid understanding of the circuit design techniques in the remainder of the book. Static CMOS logic design is given an in-depth treatment which covers both the analysis and design of these types of circuits. Emphasis is on analyzing circuits to understand the relationship between the design and performance in an integrated environment. Analytic models and their application are presented to provide a uniform base for the design philosophy developed in the study. Dynamic circuit concepts such as charge sharing and charge leakage are presented in detail and then applied to dynamic logic families such as domino cascades, self-resetting logic, and dynamic single-phase designs. Differential logic families are given an entire chapter that discusses CVSL, CPL, and related design styles. Chip issues such as interconnect modeling, crosstalk, and input/output circuits round out the coverage. CMOS Logic Circuit Design provides the reader with an opportunity to see the field in a unified manner that emphasizes solving design problems using the various logic styles available in CMOS. CMOS Logic Circuit Design is designed to be used as both a textbook (either in the classroom or for self-study) and as a reference for the VLSI chip designer |
Beschreibung: | 1 Online-Ressource (XX, 528 p) |
ISBN: | 9780306475290 |
DOI: | 10.1007/b117409 |
Internformat
MARC
LEADER | 00000nmm a2200000zc 4500 | ||
---|---|---|---|
001 | BV045148485 | ||
003 | DE-604 | ||
005 | 00000000000000.0 | ||
007 | cr|uuu---uuuuu | ||
008 | 180827s2001 |||| o||u| ||||||eng d | ||
020 | |a 9780306475290 |9 978-0-306-47529-0 | ||
024 | 7 | |a 10.1007/b117409 |2 doi | |
035 | |a (ZDB-2-ENG)978-0-306-47529-0 | ||
035 | |a (OCoLC)1050950525 | ||
035 | |a (DE-599)BVBBV045148485 | ||
040 | |a DE-604 |b ger |e aacr | ||
041 | 0 | |a eng | |
049 | |a DE-573 |a DE-634 | ||
082 | 0 | |a 621.381 |2 23 | |
084 | |a ZN 4960 |0 (DE-625)157426: |2 rvk | ||
100 | 1 | |a Uyemura, John P. |e Verfasser |4 aut | |
245 | 1 | 0 | |a CMOS Logic Circuit Design |c by John P. Uyemura |
264 | 1 | |a Boston, MA |b Springer US |c 2001 | |
300 | |a 1 Online-Ressource (XX, 528 p) | ||
336 | |b txt |2 rdacontent | ||
337 | |b c |2 rdamedia | ||
338 | |b cr |2 rdacarrier | ||
520 | |a CMOS Logic Circuit Design is an up-to-date treatment of the analysis and design of CMOS integrated digital logic circuits. It is a self- contained treatment that covers all of the important digital circuit design styles found in modern CMOS chips. Introductory chapters on MOSFET physics and CMOS fabrication provide the background needed for a solid understanding of the circuit design techniques in the remainder of the book. Static CMOS logic design is given an in-depth treatment which covers both the analysis and design of these types of circuits. Emphasis is on analyzing circuits to understand the relationship between the design and performance in an integrated environment. Analytic models and their application are presented to provide a uniform base for the design philosophy developed in the study. Dynamic circuit concepts such as charge sharing and charge leakage are presented in detail and then applied to dynamic logic families such as domino cascades, self-resetting logic, and dynamic single-phase designs. Differential logic families are given an entire chapter that discusses CVSL, CPL, and related design styles. Chip issues such as interconnect modeling, crosstalk, and input/output circuits round out the coverage. CMOS Logic Circuit Design provides the reader with an opportunity to see the field in a unified manner that emphasizes solving design problems using the various logic styles available in CMOS. CMOS Logic Circuit Design is designed to be used as both a textbook (either in the classroom or for self-study) and as a reference for the VLSI chip designer | ||
650 | 4 | |a Engineering | |
650 | 4 | |a Electronics and Microelectronics, Instrumentation | |
650 | 4 | |a Circuits and Systems | |
650 | 4 | |a Electrical Engineering | |
650 | 4 | |a Engineering | |
650 | 4 | |a Electrical engineering | |
650 | 4 | |a Electronics | |
650 | 4 | |a Microelectronics | |
650 | 4 | |a Electronic circuits | |
650 | 0 | 7 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Logische Schaltung |0 (DE-588)4131023-8 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Digitale integrierte Schaltung |0 (DE-588)4113313-4 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a CMOS |0 (DE-588)4010319-5 |2 gnd |9 rswk-swf |
650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
689 | 0 | 0 | |a Logische Schaltung |0 (DE-588)4131023-8 |D s |
689 | 0 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
689 | 0 | 2 | |a CMOS |0 (DE-588)4010319-5 |D s |
689 | 0 | |8 1\p |5 DE-604 | |
689 | 1 | 0 | |a CMOS-Schaltung |0 (DE-588)4148111-2 |D s |
689 | 1 | 1 | |a VLSI |0 (DE-588)4117388-0 |D s |
689 | 1 | 2 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
689 | 1 | |8 2\p |5 DE-604 | |
689 | 2 | 0 | |a CMOS |0 (DE-588)4010319-5 |D s |
689 | 2 | 1 | |a Digitale integrierte Schaltung |0 (DE-588)4113313-4 |D s |
689 | 2 | |8 3\p |5 DE-604 | |
776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |z 9780792384526 |
856 | 4 | 0 | |u https://doi.org/10.1007/b117409 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
912 | |a ZDB-2-ENG | ||
940 | 1 | |q ZDB-2-ENG_2000/2004 | |
999 | |a oai:aleph.bib-bvb.de:BVB01-030538184 | ||
883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
966 | e | |u https://doi.org/10.1007/b117409 |l FHI01 |p ZDB-2-ENG |q ZDB-2-ENG_2000/2004 |x Verlag |3 Volltext | |
966 | e | |u https://doi.org/10.1007/b117409 |l BTU01 |p ZDB-2-ENG |q ZDB-2-ENG_Archiv |x Verlag |3 Volltext |
Datensatz im Suchindex
_version_ | 1804178818506686464 |
---|---|
any_adam_object | |
author | Uyemura, John P. |
author_facet | Uyemura, John P. |
author_role | aut |
author_sort | Uyemura, John P. |
author_variant | j p u jp jpu |
building | Verbundindex |
bvnumber | BV045148485 |
classification_rvk | ZN 4960 |
collection | ZDB-2-ENG |
ctrlnum | (ZDB-2-ENG)978-0-306-47529-0 (OCoLC)1050950525 (DE-599)BVBBV045148485 |
dewey-full | 621.381 |
dewey-hundreds | 600 - Technology (Applied sciences) |
dewey-ones | 621 - Applied physics |
dewey-raw | 621.381 |
dewey-search | 621.381 |
dewey-sort | 3621.381 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
doi_str_mv | 10.1007/b117409 |
format | Electronic eBook |
fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>04464nmm a2200745zc 4500</leader><controlfield tag="001">BV045148485</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180827s2001 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780306475290</subfield><subfield code="9">978-0-306-47529-0</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/b117409</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-0-306-47529-0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)1050950525</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV045148485</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-573</subfield><subfield code="a">DE-634</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.381</subfield><subfield code="2">23</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4960</subfield><subfield code="0">(DE-625)157426:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Uyemura, John P.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">CMOS Logic Circuit Design</subfield><subfield code="c">by John P. Uyemura</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">2001</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XX, 528 p)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">CMOS Logic Circuit Design is an up-to-date treatment of the analysis and design of CMOS integrated digital logic circuits. It is a self- contained treatment that covers all of the important digital circuit design styles found in modern CMOS chips. Introductory chapters on MOSFET physics and CMOS fabrication provide the background needed for a solid understanding of the circuit design techniques in the remainder of the book. Static CMOS logic design is given an in-depth treatment which covers both the analysis and design of these types of circuits. Emphasis is on analyzing circuits to understand the relationship between the design and performance in an integrated environment. Analytic models and their application are presented to provide a uniform base for the design philosophy developed in the study. Dynamic circuit concepts such as charge sharing and charge leakage are presented in detail and then applied to dynamic logic families such as domino cascades, self-resetting logic, and dynamic single-phase designs. Differential logic families are given an entire chapter that discusses CVSL, CPL, and related design styles. Chip issues such as interconnect modeling, crosstalk, and input/output circuits round out the coverage. CMOS Logic Circuit Design provides the reader with an opportunity to see the field in a unified manner that emphasizes solving design problems using the various logic styles available in CMOS. CMOS Logic Circuit Design is designed to be used as both a textbook (either in the classroom or for self-study) and as a reference for the VLSI chip designer</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics and Microelectronics, Instrumentation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electrical engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Microelectronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CMOS-Schaltung</subfield><subfield code="0">(DE-588)4148111-2</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Digitale integrierte Schaltung</subfield><subfield code="0">(DE-588)4113313-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">CMOS</subfield><subfield code="0">(DE-588)4010319-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Logische Schaltung</subfield><subfield code="0">(DE-588)4131023-8</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">Entwurf</subfield><subfield code="0">(DE-588)4121208-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">CMOS</subfield><subfield code="0">(DE-588)4010319-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">CMOS-Schaltung</subfield><subfield code="0">(DE-588)4148111-2</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="1"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2="2"><subfield code="a">Schaltungsentwurf</subfield><subfield code="0">(DE-588)4179389-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">CMOS</subfield><subfield code="0">(DE-588)4010319-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2="1"><subfield code="a">Digitale integrierte Schaltung</subfield><subfield code="0">(DE-588)4113313-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="8">3\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="z">9780792384526</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/b117409</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_2000/2004</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030538184</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">2\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">3\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/b117409</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_2000/2004</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/b117409</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="q">ZDB-2-ENG_Archiv</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
id | DE-604.BV045148485 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T08:10:01Z |
institution | BVB |
isbn | 9780306475290 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030538184 |
oclc_num | 1050950525 |
open_access_boolean | |
owner | DE-573 DE-634 |
owner_facet | DE-573 DE-634 |
physical | 1 Online-Ressource (XX, 528 p) |
psigel | ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_2000/2004 ZDB-2-ENG ZDB-2-ENG_Archiv |
publishDate | 2001 |
publishDateSearch | 2001 |
publishDateSort | 2001 |
publisher | Springer US |
record_format | marc |
spelling | Uyemura, John P. Verfasser aut CMOS Logic Circuit Design by John P. Uyemura Boston, MA Springer US 2001 1 Online-Ressource (XX, 528 p) txt rdacontent c rdamedia cr rdacarrier CMOS Logic Circuit Design is an up-to-date treatment of the analysis and design of CMOS integrated digital logic circuits. It is a self- contained treatment that covers all of the important digital circuit design styles found in modern CMOS chips. Introductory chapters on MOSFET physics and CMOS fabrication provide the background needed for a solid understanding of the circuit design techniques in the remainder of the book. Static CMOS logic design is given an in-depth treatment which covers both the analysis and design of these types of circuits. Emphasis is on analyzing circuits to understand the relationship between the design and performance in an integrated environment. Analytic models and their application are presented to provide a uniform base for the design philosophy developed in the study. Dynamic circuit concepts such as charge sharing and charge leakage are presented in detail and then applied to dynamic logic families such as domino cascades, self-resetting logic, and dynamic single-phase designs. Differential logic families are given an entire chapter that discusses CVSL, CPL, and related design styles. Chip issues such as interconnect modeling, crosstalk, and input/output circuits round out the coverage. CMOS Logic Circuit Design provides the reader with an opportunity to see the field in a unified manner that emphasizes solving design problems using the various logic styles available in CMOS. CMOS Logic Circuit Design is designed to be used as both a textbook (either in the classroom or for self-study) and as a reference for the VLSI chip designer Engineering Electronics and Microelectronics, Instrumentation Circuits and Systems Electrical Engineering Electrical engineering Electronics Microelectronics Electronic circuits CMOS-Schaltung (DE-588)4148111-2 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 gnd rswk-swf Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf CMOS (DE-588)4010319-5 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf Logische Schaltung (DE-588)4131023-8 s Entwurf (DE-588)4121208-3 s CMOS (DE-588)4010319-5 s 1\p DE-604 CMOS-Schaltung (DE-588)4148111-2 s VLSI (DE-588)4117388-0 s Schaltungsentwurf (DE-588)4179389-4 s 2\p DE-604 Digitale integrierte Schaltung (DE-588)4113313-4 s 3\p DE-604 Erscheint auch als Druck-Ausgabe 9780792384526 https://doi.org/10.1007/b117409 Verlag URL des Erstveröffentlichers Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | Uyemura, John P. CMOS Logic Circuit Design Engineering Electronics and Microelectronics, Instrumentation Circuits and Systems Electrical Engineering Electrical engineering Electronics Microelectronics Electronic circuits CMOS-Schaltung (DE-588)4148111-2 gnd VLSI (DE-588)4117388-0 gnd Logische Schaltung (DE-588)4131023-8 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd Entwurf (DE-588)4121208-3 gnd CMOS (DE-588)4010319-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
subject_GND | (DE-588)4148111-2 (DE-588)4117388-0 (DE-588)4131023-8 (DE-588)4113313-4 (DE-588)4121208-3 (DE-588)4010319-5 (DE-588)4179389-4 |
title | CMOS Logic Circuit Design |
title_auth | CMOS Logic Circuit Design |
title_exact_search | CMOS Logic Circuit Design |
title_full | CMOS Logic Circuit Design by John P. Uyemura |
title_fullStr | CMOS Logic Circuit Design by John P. Uyemura |
title_full_unstemmed | CMOS Logic Circuit Design by John P. Uyemura |
title_short | CMOS Logic Circuit Design |
title_sort | cmos logic circuit design |
topic | Engineering Electronics and Microelectronics, Instrumentation Circuits and Systems Electrical Engineering Electrical engineering Electronics Microelectronics Electronic circuits CMOS-Schaltung (DE-588)4148111-2 gnd VLSI (DE-588)4117388-0 gnd Logische Schaltung (DE-588)4131023-8 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd Entwurf (DE-588)4121208-3 gnd CMOS (DE-588)4010319-5 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
topic_facet | Engineering Electronics and Microelectronics, Instrumentation Circuits and Systems Electrical Engineering Electrical engineering Electronics Microelectronics Electronic circuits CMOS-Schaltung VLSI Logische Schaltung Digitale integrierte Schaltung Entwurf CMOS Schaltungsentwurf |
url | https://doi.org/10.1007/b117409 |
work_keys_str_mv | AT uyemurajohnp cmoslogiccircuitdesign |