Verification by error modeling: using testing techniques in hardware verification
Saved in:
| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston
Kluwer Academic Publishers
2003
|
| Series: | Frontiers in electronic testing
25 |
| Subjects: | |
| Physical Description: | xiv, 216 p. |
| ISBN: | 1402076525 |
Staff View
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| 245 | 1 | 0 | |a Verification by error modeling |b using testing techniques in hardware verification |c written by Katarzyna Radecka, Zeljko Zilic |
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| 300 | |a xiv, 216 p. | ||
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| 490 | 0 | |a Frontiers in electronic testing |v 25 | |
| 505 | 8 | |a Includes bibliographical references and index | |
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| 650 | 4 | |a Integrated circuits |x Verification | |
| 650 | 4 | |a Error analysis (Mathematics) | |
| 700 | 1 | |a Zilic, Zeljko |e Sonstige |4 oth | |
| 912 | |a ZDB-38-ESG | ||
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Record in the Search Index
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|---|---|
| any_adam_object | |
| author | Radecka, Katarzyna |
| author_facet | Radecka, Katarzyna |
| author_role | aut |
| author_sort | Radecka, Katarzyna |
| author_variant | k r kr |
| building | Verbundindex |
| bvnumber | BV044833811 |
| collection | ZDB-38-ESG |
| contents | Includes bibliographical references and index |
| ctrlnum | (ZDB-38-ESG)ebr10088540 (OCoLC)228118912 (DE-599)BVBBV044833811 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:02:21Z |
| institution | BVB |
| isbn | 1402076525 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030228674 |
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| physical | xiv, 216 p. |
| psigel | ZDB-38-ESG |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Kluwer Academic Publishers |
| record_format | marc |
| series2 | Frontiers in electronic testing |
| spelling | Radecka, Katarzyna Verfasser aut Verification by error modeling using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic Boston Kluwer Academic Publishers 2003 xiv, 216 p. txt rdacontent c rdamedia cr rdacarrier Frontiers in electronic testing 25 Includes bibliographical references and index Integrated circuits Very large scale integration Computer-aided design Integrated circuits Verification Error analysis (Mathematics) Zilic, Zeljko Sonstige oth |
| spellingShingle | Radecka, Katarzyna Verification by error modeling using testing techniques in hardware verification Includes bibliographical references and index Integrated circuits Very large scale integration Computer-aided design Integrated circuits Verification Error analysis (Mathematics) |
| title | Verification by error modeling using testing techniques in hardware verification |
| title_auth | Verification by error modeling using testing techniques in hardware verification |
| title_exact_search | Verification by error modeling using testing techniques in hardware verification |
| title_full | Verification by error modeling using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic |
| title_fullStr | Verification by error modeling using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic |
| title_full_unstemmed | Verification by error modeling using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic |
| title_short | Verification by error modeling |
| title_sort | verification by error modeling using testing techniques in hardware verification |
| title_sub | using testing techniques in hardware verification |
| topic | Integrated circuits Very large scale integration Computer-aided design Integrated circuits Verification Error analysis (Mathematics) |
| topic_facet | Integrated circuits Very large scale integration Computer-aided design Integrated circuits Verification Error analysis (Mathematics) |
| work_keys_str_mv | AT radeckakatarzyna verificationbyerrormodelingusingtestingtechniquesinhardwareverification AT ziliczeljko verificationbyerrormodelingusingtestingtechniquesinhardwareverification |