Verification by error modeling: using testing techniques in hardware verification
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston
Kluwer Academic Publishers
2003
|
| Schriftenreihe: | Frontiers in electronic testing
25 |
| Schlagworte: | |
| Beschreibung: | xiv, 216 p. |
| ISBN: | 1402076525 |
Internformat
MARC
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| 008 | 180305s2003 |||| o||u| ||||||eng d | ||
| 020 | |a 1402076525 |c alk. paper |9 1-4020-7652-5 | ||
| 035 | |a (ZDB-38-ESG)ebr10088540 | ||
| 035 | |a (OCoLC)228118912 | ||
| 035 | |a (DE-599)BVBBV044833811 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.39/5 |2 22 | |
| 100 | 1 | |a Radecka, Katarzyna |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Verification by error modeling |b using testing techniques in hardware verification |c written by Katarzyna Radecka, Zeljko Zilic |
| 264 | 1 | |a Boston |b Kluwer Academic Publishers |c 2003 | |
| 300 | |a xiv, 216 p. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a Frontiers in electronic testing |v 25 | |
| 505 | 8 | |a Includes bibliographical references and index | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Computer-aided design | |
| 650 | 4 | |a Integrated circuits |x Verification | |
| 650 | 4 | |a Error analysis (Mathematics) | |
| 700 | 1 | |a Zilic, Zeljko |e Sonstige |4 oth | |
| 912 | |a ZDB-38-ESG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030228674 | ||
Datensatz im Suchindex
| _version_ | 1804178336554942464 |
|---|---|
| any_adam_object | |
| author | Radecka, Katarzyna |
| author_facet | Radecka, Katarzyna |
| author_role | aut |
| author_sort | Radecka, Katarzyna |
| author_variant | k r kr |
| building | Verbundindex |
| bvnumber | BV044833811 |
| collection | ZDB-38-ESG |
| contents | Includes bibliographical references and index |
| ctrlnum | (ZDB-38-ESG)ebr10088540 (OCoLC)228118912 (DE-599)BVBBV044833811 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV044833811 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:02:21Z |
| institution | BVB |
| isbn | 1402076525 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030228674 |
| oclc_num | 228118912 |
| open_access_boolean | |
| physical | xiv, 216 p. |
| psigel | ZDB-38-ESG |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Kluwer Academic Publishers |
| record_format | marc |
| series2 | Frontiers in electronic testing |
| spelling | Radecka, Katarzyna Verfasser aut Verification by error modeling using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic Boston Kluwer Academic Publishers 2003 xiv, 216 p. txt rdacontent c rdamedia cr rdacarrier Frontiers in electronic testing 25 Includes bibliographical references and index Integrated circuits Very large scale integration Computer-aided design Integrated circuits Verification Error analysis (Mathematics) Zilic, Zeljko Sonstige oth |
| spellingShingle | Radecka, Katarzyna Verification by error modeling using testing techniques in hardware verification Includes bibliographical references and index Integrated circuits Very large scale integration Computer-aided design Integrated circuits Verification Error analysis (Mathematics) |
| title | Verification by error modeling using testing techniques in hardware verification |
| title_auth | Verification by error modeling using testing techniques in hardware verification |
| title_exact_search | Verification by error modeling using testing techniques in hardware verification |
| title_full | Verification by error modeling using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic |
| title_fullStr | Verification by error modeling using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic |
| title_full_unstemmed | Verification by error modeling using testing techniques in hardware verification written by Katarzyna Radecka, Zeljko Zilic |
| title_short | Verification by error modeling |
| title_sort | verification by error modeling using testing techniques in hardware verification |
| title_sub | using testing techniques in hardware verification |
| topic | Integrated circuits Very large scale integration Computer-aided design Integrated circuits Verification Error analysis (Mathematics) |
| topic_facet | Integrated circuits Very large scale integration Computer-aided design Integrated circuits Verification Error analysis (Mathematics) |
| work_keys_str_mv | AT radeckakatarzyna verificationbyerrormodelingusingtestingtechniquesinhardwareverification AT ziliczeljko verificationbyerrormodelingusingtestingtechniquesinhardwareverification |