System level design model with re-use of system IP:
Gespeichert in:
| Format: | Elektronisch E-Book |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Boston
Kluwer Academic Publishers
c2003
|
| Schlagworte: | |
| Beschreibung: | 211 p. |
| ISBN: | 1402075944 |
Internformat
MARC
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| 245 | 1 | 0 | |a System level design model with re-use of system IP |c edited by Patrizia Cavalloro ... [et al.] |
| 264 | 1 | |a Boston |b Kluwer Academic Publishers |c c2003 | |
| 300 | |a 211 p. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 505 | 8 | |a Includes bibliographical references | |
| 650 | 4 | |a Systems on a chip |x Design and construction | |
| 650 | 4 | |a Modularity (Engineering) | |
| 650 | 4 | |a System design | |
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| 650 | 0 | 7 | |a Eingebettetes System |0 (DE-588)4396978-1 |2 gnd |9 rswk-swf |
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| 689 | 0 | 0 | |a Eingebettetes System |0 (DE-588)4396978-1 |D s |
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| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
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| building | Verbundindex |
| bvnumber | BV044833299 |
| collection | ZDB-38-ESG |
| contents | Includes bibliographical references |
| ctrlnum | (ZDB-38-ESG)ebr10078634 (OCoLC)228114207 (DE-599)BVBBV044833299 |
| format | Electronic eBook |
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| id | DE-604.BV044833299 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:02:20Z |
| institution | BVB |
| isbn | 1402075944 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030228162 |
| oclc_num | 228114207 |
| open_access_boolean | |
| physical | 211 p. |
| psigel | ZDB-38-ESG |
| publishDate | 2003 |
| publishDateSearch | 2003 |
| publishDateSort | 2003 |
| publisher | Kluwer Academic Publishers |
| record_format | marc |
| spelling | System level design model with re-use of system IP edited by Patrizia Cavalloro ... [et al.] Boston Kluwer Academic Publishers c2003 211 p. txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references Systems on a chip Design and construction Modularity (Engineering) System design Formale Spezifikationstechnik (DE-588)4299725-2 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Hardwareentwurf (DE-588)4159103-3 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 s Hardwareentwurf (DE-588)4159103-3 s Formale Spezifikationstechnik (DE-588)4299725-2 s 1\p DE-604 Cavalloro, Patrizia Sonstige oth 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | System level design model with re-use of system IP Includes bibliographical references Systems on a chip Design and construction Modularity (Engineering) System design Formale Spezifikationstechnik (DE-588)4299725-2 gnd Eingebettetes System (DE-588)4396978-1 gnd Hardwareentwurf (DE-588)4159103-3 gnd |
| subject_GND | (DE-588)4299725-2 (DE-588)4396978-1 (DE-588)4159103-3 |
| title | System level design model with re-use of system IP |
| title_auth | System level design model with re-use of system IP |
| title_exact_search | System level design model with re-use of system IP |
| title_full | System level design model with re-use of system IP edited by Patrizia Cavalloro ... [et al.] |
| title_fullStr | System level design model with re-use of system IP edited by Patrizia Cavalloro ... [et al.] |
| title_full_unstemmed | System level design model with re-use of system IP edited by Patrizia Cavalloro ... [et al.] |
| title_short | System level design model with re-use of system IP |
| title_sort | system level design model with re use of system ip |
| topic | Systems on a chip Design and construction Modularity (Engineering) System design Formale Spezifikationstechnik (DE-588)4299725-2 gnd Eingebettetes System (DE-588)4396978-1 gnd Hardwareentwurf (DE-588)4159103-3 gnd |
| topic_facet | Systems on a chip Design and construction Modularity (Engineering) System design Formale Spezifikationstechnik Eingebettetes System Hardwareentwurf |
| work_keys_str_mv | AT cavalloropatrizia systemleveldesignmodelwithreuseofsystemip |