Principles of verifiable RTL design: a functional coding style supporting verification processes in Verilog
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
New York
Kluwer Academic
c2002
|
| Ausgabe: | 2nd ed |
| Schlagworte: | |
| Beschreibung: | xxiv, 281 p. |
| ISBN: | 0306476312 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV044831104 | ||
| 003 | DE-604 | ||
| 005 | 20180305 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 180305s2002 |||| o||u| ||||||eng d | ||
| 020 | |a 0306476312 |9 0-306-47631-2 | ||
| 035 | |a (ZDB-38-ESG)ebr10053381 | ||
| 035 | |a (OCoLC)70755619 | ||
| 035 | |a (DE-599)BVBBV044831104 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 100 | 1 | |a Bening, Lionel |d 1939- |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Principles of verifiable RTL design |b a functional coding style supporting verification processes in Verilog |c Lionel Bening and Harry Foster |
| 250 | |a 2nd ed | ||
| 264 | 1 | |a New York |b Kluwer Academic |c c2002 | |
| 300 | |a xxiv, 281 p. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 505 | 8 | |a Includes bibliographical references and index | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Computer-aided design | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 650 | 4 | |a Electronic digital computers |x Computer-aided design | |
| 650 | 0 | 7 | |a Register-Transfer-Ebene |0 (DE-588)4215789-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Register-Transfer-Ebene |0 (DE-588)4215789-4 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 700 | 1 | |a Foster, Harry |d 1956- |e Sonstige |4 oth | |
| 912 | |a ZDB-38-ESG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030225967 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804178332276752384 |
|---|---|
| any_adam_object | |
| author | Bening, Lionel 1939- |
| author_facet | Bening, Lionel 1939- |
| author_role | aut |
| author_sort | Bening, Lionel 1939- |
| author_variant | l b lb |
| building | Verbundindex |
| bvnumber | BV044831104 |
| collection | ZDB-38-ESG |
| contents | Includes bibliographical references and index |
| ctrlnum | (ZDB-38-ESG)ebr10053381 (OCoLC)70755619 (DE-599)BVBBV044831104 |
| edition | 2nd ed |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01453nmm a2200385zc 4500</leader><controlfield tag="001">BV044831104</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20180305 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">180305s2002 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0306476312</subfield><subfield code="9">0-306-47631-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-38-ESG)ebr10053381</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)70755619</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV044831104</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Bening, Lionel</subfield><subfield code="d">1939-</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Principles of verifiable RTL design</subfield><subfield code="b">a functional coding style supporting verification processes in Verilog</subfield><subfield code="c">Lionel Bening and Harry Foster</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">2nd ed</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York</subfield><subfield code="b">Kluwer Academic</subfield><subfield code="c">c2002</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">xxiv, 281 p.</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Very large scale integration</subfield><subfield code="x">Computer-aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog (Computer hardware description language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic digital computers</subfield><subfield code="x">Computer-aided design</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Register-Transfer-Ebene</subfield><subfield code="0">(DE-588)4215789-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Register-Transfer-Ebene</subfield><subfield code="0">(DE-588)4215789-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Foster, Harry</subfield><subfield code="d">1956-</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-38-ESG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-030225967</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| id | DE-604.BV044831104 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:02:17Z |
| institution | BVB |
| isbn | 0306476312 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030225967 |
| oclc_num | 70755619 |
| open_access_boolean | |
| physical | xxiv, 281 p. |
| psigel | ZDB-38-ESG |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | Kluwer Academic |
| record_format | marc |
| spelling | Bening, Lionel 1939- Verfasser aut Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Lionel Bening and Harry Foster 2nd ed New York Kluwer Academic c2002 xxiv, 281 p. txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index Integrated circuits Very large scale integration Computer-aided design Verilog (Computer hardware description language) Electronic digital computers Computer-aided design Register-Transfer-Ebene (DE-588)4215789-4 gnd rswk-swf Register-Transfer-Ebene (DE-588)4215789-4 s 1\p DE-604 Foster, Harry 1956- Sonstige oth 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Bening, Lionel 1939- Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Includes bibliographical references and index Integrated circuits Very large scale integration Computer-aided design Verilog (Computer hardware description language) Electronic digital computers Computer-aided design Register-Transfer-Ebene (DE-588)4215789-4 gnd |
| subject_GND | (DE-588)4215789-4 |
| title | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog |
| title_auth | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog |
| title_exact_search | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog |
| title_full | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Lionel Bening and Harry Foster |
| title_fullStr | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Lionel Bening and Harry Foster |
| title_full_unstemmed | Principles of verifiable RTL design a functional coding style supporting verification processes in Verilog Lionel Bening and Harry Foster |
| title_short | Principles of verifiable RTL design |
| title_sort | principles of verifiable rtl design a functional coding style supporting verification processes in verilog |
| title_sub | a functional coding style supporting verification processes in Verilog |
| topic | Integrated circuits Very large scale integration Computer-aided design Verilog (Computer hardware description language) Electronic digital computers Computer-aided design Register-Transfer-Ebene (DE-588)4215789-4 gnd |
| topic_facet | Integrated circuits Very large scale integration Computer-aided design Verilog (Computer hardware description language) Electronic digital computers Computer-aided design Register-Transfer-Ebene |
| work_keys_str_mv | AT beninglionel principlesofverifiablertldesignafunctionalcodingstylesupportingverificationprocessesinverilog AT fosterharry principlesofverifiablertldesignafunctionalcodingstylesupportingverificationprocessesinverilog |