Logic synthesis and verification algorithms:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston
Kluwer Academic
c2002, 1996
|
| Schlagworte: | |
| Beschreibung: | xxxii, 597 p. |
| ISBN: | 0306475928 0792397460 |
Internformat
MARC
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| 100 | 1 | |a Hachtel, Gary D. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Logic synthesis and verification algorithms |c by Gary D. Hachtel, Fabio Somenzi |
| 264 | 1 | |a Boston |b Kluwer Academic |c c2002, 1996 | |
| 300 | |a xxxii, 597 p. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 505 | 8 | |a Includes bibliographical references and index | |
| 650 | 4 | |a Computer-aided design | |
| 650 | 4 | |a Integrated circuits |x Verification | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design and construction |x Data processing | |
| 650 | 4 | |a Logic design |x Data processing | |
| 650 | 0 | 7 | |a Logiksynthese |0 (DE-588)4348178-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Logischer Entwurf |0 (DE-588)4168051-0 |2 gnd |9 rswk-swf |
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| 689 | 1 | |8 2\p |5 DE-604 | |
| 700 | 1 | |a Somenzi, Fabio |e Sonstige |4 oth | |
| 912 | |a ZDB-38-ESG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-030225930 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
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| author | Hachtel, Gary D. |
| author_facet | Hachtel, Gary D. |
| author_role | aut |
| author_sort | Hachtel, Gary D. |
| author_variant | g d h gd gdh |
| building | Verbundindex |
| bvnumber | BV044831066 |
| collection | ZDB-38-ESG |
| contents | Includes bibliographical references and index |
| ctrlnum | (ZDB-38-ESG)ebr10053328 (OCoLC)70757204 (DE-599)BVBBV044831066 |
| format | Electronic eBook |
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| id | DE-604.BV044831066 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:02:17Z |
| institution | BVB |
| isbn | 0306475928 0792397460 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030225930 |
| oclc_num | 70757204 |
| open_access_boolean | |
| physical | xxxii, 597 p. |
| psigel | ZDB-38-ESG |
| publishDate | 2002 |
| publishDateSearch | 2002 |
| publishDateSort | 2002 |
| publisher | Kluwer Academic |
| record_format | marc |
| spelling | Hachtel, Gary D. Verfasser aut Logic synthesis and verification algorithms by Gary D. Hachtel, Fabio Somenzi Boston Kluwer Academic c2002, 1996 xxxii, 597 p. txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index Computer-aided design Integrated circuits Verification Integrated circuits Very large scale integration Design and construction Data processing Logic design Data processing Logiksynthese (DE-588)4348178-4 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 gnd rswk-swf Logischer Entwurf (DE-588)4168051-0 s 1\p DE-604 Logiksynthese (DE-588)4348178-4 s 2\p DE-604 Somenzi, Fabio Sonstige oth 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Hachtel, Gary D. Logic synthesis and verification algorithms Includes bibliographical references and index Computer-aided design Integrated circuits Verification Integrated circuits Very large scale integration Design and construction Data processing Logic design Data processing Logiksynthese (DE-588)4348178-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| subject_GND | (DE-588)4348178-4 (DE-588)4168051-0 |
| title | Logic synthesis and verification algorithms |
| title_auth | Logic synthesis and verification algorithms |
| title_exact_search | Logic synthesis and verification algorithms |
| title_full | Logic synthesis and verification algorithms by Gary D. Hachtel, Fabio Somenzi |
| title_fullStr | Logic synthesis and verification algorithms by Gary D. Hachtel, Fabio Somenzi |
| title_full_unstemmed | Logic synthesis and verification algorithms by Gary D. Hachtel, Fabio Somenzi |
| title_short | Logic synthesis and verification algorithms |
| title_sort | logic synthesis and verification algorithms |
| topic | Computer-aided design Integrated circuits Verification Integrated circuits Very large scale integration Design and construction Data processing Logic design Data processing Logiksynthese (DE-588)4348178-4 gnd Logischer Entwurf (DE-588)4168051-0 gnd |
| topic_facet | Computer-aided design Integrated circuits Verification Integrated circuits Very large scale integration Design and construction Data processing Logic design Data processing Logiksynthese Logischer Entwurf |
| work_keys_str_mv | AT hachtelgaryd logicsynthesisandverificationalgorithms AT somenzifabio logicsynthesisandverificationalgorithms |