Algorithms for VLSI physical design automation:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston
Kluwer Academic Publishers
c1999
|
| Ausgabe: | 3rd ed |
| Schlagworte: | |
| Beschreibung: | xxx, 572 p. |
| ISBN: | 0792383931 |
Internformat
MARC
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| 008 | 180305s1999 |||| o||u| ||||||eng d | ||
| 020 | |a 0792383931 |c alk. paper |9 0-7923-8393-1 | ||
| 035 | |a (ZDB-38-ESG)ebr10052687 | ||
| 035 | |a (OCoLC)559384701 | ||
| 035 | |a (DE-599)BVBBV044830907 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.39/5 |2 21 | |
| 100 | 1 | |a Sherwani, N. A. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Algorithms for VLSI physical design automation |c Naveed A. Sherwani |
| 250 | |a 3rd ed | ||
| 264 | 1 | |a Boston |b Kluwer Academic Publishers |c c1999 | |
| 300 | |a xxx, 572 p. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 505 | 8 | |a Includes bibliographical references (p. [525]-561) and indexes | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Computer-aided design | |
| 650 | 4 | |a Algorithms | |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Algorithmus |0 (DE-588)4001183-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Entwurf |0 (DE-588)4121208-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a Entwurf |0 (DE-588)4121208-3 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 689 | 1 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 1 | 1 | |a Algorithmus |0 (DE-588)4001183-5 |D s |
| 689 | 1 | |8 2\p |5 DE-604 | |
| 689 | 2 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 2 | 1 | |a Schaltungsentwurf |0 (DE-588)4179389-4 |D s |
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| 883 | 1 | |8 2\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 883 | 1 | |8 3\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804178331927576576 |
|---|---|
| any_adam_object | |
| author | Sherwani, N. A. |
| author_facet | Sherwani, N. A. |
| author_role | aut |
| author_sort | Sherwani, N. A. |
| author_variant | n a s na nas |
| building | Verbundindex |
| bvnumber | BV044830907 |
| collection | ZDB-38-ESG |
| contents | Includes bibliographical references (p. [525]-561) and indexes |
| ctrlnum | (ZDB-38-ESG)ebr10052687 (OCoLC)559384701 (DE-599)BVBBV044830907 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| edition | 3rd ed |
| format | Electronic eBook |
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| id | DE-604.BV044830907 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T08:02:17Z |
| institution | BVB |
| isbn | 0792383931 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030225772 |
| oclc_num | 559384701 |
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| physical | xxx, 572 p. |
| psigel | ZDB-38-ESG |
| publishDate | 1999 |
| publishDateSearch | 1999 |
| publishDateSort | 1999 |
| publisher | Kluwer Academic Publishers |
| record_format | marc |
| spelling | Sherwani, N. A. Verfasser aut Algorithms for VLSI physical design automation Naveed A. Sherwani 3rd ed Boston Kluwer Academic Publishers c1999 xxx, 572 p. txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references (p. [525]-561) and indexes Integrated circuits Very large scale integration Computer-aided design Algorithms VLSI (DE-588)4117388-0 gnd rswk-swf Algorithmus (DE-588)4001183-5 gnd rswk-swf Entwurf (DE-588)4121208-3 gnd rswk-swf Schaltungsentwurf (DE-588)4179389-4 gnd rswk-swf VLSI (DE-588)4117388-0 s Entwurf (DE-588)4121208-3 s 1\p DE-604 Algorithmus (DE-588)4001183-5 s 2\p DE-604 Schaltungsentwurf (DE-588)4179389-4 s 3\p DE-604 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Sherwani, N. A. Algorithms for VLSI physical design automation Includes bibliographical references (p. [525]-561) and indexes Integrated circuits Very large scale integration Computer-aided design Algorithms VLSI (DE-588)4117388-0 gnd Algorithmus (DE-588)4001183-5 gnd Entwurf (DE-588)4121208-3 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4001183-5 (DE-588)4121208-3 (DE-588)4179389-4 |
| title | Algorithms for VLSI physical design automation |
| title_auth | Algorithms for VLSI physical design automation |
| title_exact_search | Algorithms for VLSI physical design automation |
| title_full | Algorithms for VLSI physical design automation Naveed A. Sherwani |
| title_fullStr | Algorithms for VLSI physical design automation Naveed A. Sherwani |
| title_full_unstemmed | Algorithms for VLSI physical design automation Naveed A. Sherwani |
| title_short | Algorithms for VLSI physical design automation |
| title_sort | algorithms for vlsi physical design automation |
| topic | Integrated circuits Very large scale integration Computer-aided design Algorithms VLSI (DE-588)4117388-0 gnd Algorithmus (DE-588)4001183-5 gnd Entwurf (DE-588)4121208-3 gnd Schaltungsentwurf (DE-588)4179389-4 gnd |
| topic_facet | Integrated circuits Very large scale integration Computer-aided design Algorithms VLSI Algorithmus Entwurf Schaltungsentwurf |
| work_keys_str_mv | AT sherwanina algorithmsforvlsiphysicaldesignautomation |