Logic-timing simulation and the degradation delay model:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
London
Imperial College Press
c2006
|
| Schlagworte: | |
| Online-Zugang: | FHN01 Volltext |
| Beschreibung: | xvii, 267 p. ill |
| ISBN: | 1860947360 9781860947360 |
Internformat
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| 245 | 1 | 0 | |a Logic-timing simulation and the degradation delay model |c Manuel J. Bellido, Jorge Juan, Manuel Valencia |
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| 650 | 4 | |a Metal oxide semiconductors, Complementary | |
| 700 | 1 | |a Juan Chico, Jorge |e Sonstige |4 oth | |
| 700 | 1 | |a Valencia, Manuel |e Sonstige |4 oth | |
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Datensatz im Suchindex
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| author | Bellido, Manuel J. 1964- |
| author_facet | Bellido, Manuel J. 1964- |
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV044633645 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:57:43Z |
| institution | BVB |
| isbn | 1860947360 9781860947360 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-030031616 |
| oclc_num | 1012692092 |
| open_access_boolean | |
| owner | DE-92 |
| owner_facet | DE-92 |
| physical | xvii, 267 p. ill |
| psigel | ZDB-124-WOP ZDB-124-WOP FHN_PDA_WOP |
| publishDate | 2006 |
| publishDateSearch | 2006 |
| publishDateSort | 2006 |
| publisher | Imperial College Press |
| record_format | marc |
| spelling | Bellido, Manuel J. 1964- Verfasser aut Logic-timing simulation and the degradation delay model Manuel J. Bellido, Jorge Juan, Manuel Valencia London Imperial College Press c2006 xvii, 267 p. ill txt rdacontent c rdamedia cr rdacarrier Timing circuits Integrated circuits / Very large scale integration Metal oxide semiconductors, Complementary Juan Chico, Jorge Sonstige oth Valencia, Manuel Sonstige oth http://www.worldscientific.com/worldscibooks/10.1142/P411#t=toc Verlag URL des Erstveroeffentlichers Volltext |
| spellingShingle | Bellido, Manuel J. 1964- Logic-timing simulation and the degradation delay model Timing circuits Integrated circuits / Very large scale integration Metal oxide semiconductors, Complementary |
| title | Logic-timing simulation and the degradation delay model |
| title_auth | Logic-timing simulation and the degradation delay model |
| title_exact_search | Logic-timing simulation and the degradation delay model |
| title_full | Logic-timing simulation and the degradation delay model Manuel J. Bellido, Jorge Juan, Manuel Valencia |
| title_fullStr | Logic-timing simulation and the degradation delay model Manuel J. Bellido, Jorge Juan, Manuel Valencia |
| title_full_unstemmed | Logic-timing simulation and the degradation delay model Manuel J. Bellido, Jorge Juan, Manuel Valencia |
| title_short | Logic-timing simulation and the degradation delay model |
| title_sort | logic timing simulation and the degradation delay model |
| topic | Timing circuits Integrated circuits / Very large scale integration Metal oxide semiconductors, Complementary |
| topic_facet | Timing circuits Integrated circuits / Very large scale integration Metal oxide semiconductors, Complementary |
| url | http://www.worldscientific.com/worldscibooks/10.1142/P411#t=toc |
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