Symbolic parallelization of nested loop programs: = Symbolische Parallelisierung verschachtelter Schleifenprogramme
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1. Verfasser: | |
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Format: | Abschlussarbeit Buch |
Sprache: | English |
Veröffentlicht: |
Erlangen ; Nürnberg
[2017]
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Schlagworte: | |
Online-Zugang: | Inhaltsverzeichnis |
Beschreibung: | ix, 196 Seiten Illustrationen, Diagramme 21 cm |
Internformat
MARC
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100 | 1 | |a Tanase, Alexandru-Petru |e Verfasser |4 aut | |
245 | 1 | 0 | |a Symbolic parallelization of nested loop programs |b = Symbolische Parallelisierung verschachtelter Schleifenprogramme |c vorgelegt von Alexandru-Petru Tanase aus Hermannstadt, Rumänien |
246 | 1 | 3 | |a Symbolische Parallelisierung verschachtelter Schleifenprogramme |
246 | 1 | 1 | |a Symbolische Parallelisierung verschachtelter Schleifenprogramme |
264 | 1 | |a Erlangen ; Nürnberg |c [2017] | |
300 | |a ix, 196 Seiten |b Illustrationen, Diagramme |c 21 cm | ||
336 | |b txt |2 rdacontent | ||
337 | |b n |2 rdamedia | ||
338 | |b nc |2 rdacarrier | ||
502 | |b Dissertation |c Friedrich-Alexander-Universität Erlangen-Nürnberg |d 2017 | ||
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Datensatz im Suchindex
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adam_text | CONTENTS
1 INTRODUCTION 3
1.1 GOALS AND C ONTRIBUTIONS
................................................................
6
1.2 ORGANIZATION OF THE T H E SIS
.............................................................
9
2 FUNDAMENTALS AND COMPILER FRAMEWORK 11
2.1 INVASIVE COM
PUTING..........................................................................
11
2.2 INVASIVE TIGHTLY COUPLED PROCESSOR A RRA Y
S.................................. 15
2.2.1 PROCESSOR A RRA Y
...................................................................
16
2.2.2 ARRAY INTERCONNECT
.............................................................
18
2.2.3 TCPA PERIPHERALS
.............................................................
18
2.3 COMPILER FRAM EW
ORK........................................................................
20
2.3.1 COMPILATION F LOW
................................................................
21
2.3.2 FRONT E N D
.............................................................................
23
2.3.3 LOOP SPECIFICATION IN THE POLYHEDRON M O D E L
..................
25
2.3.4 PAULA LANGUAGE
................................................................
29
2.3.5 P A R O
...................................................................................
29
2.3.5.1 HIGH-LEVEL TRANSFORMATIONS
...............................
31
2.3.5.2
LOCALIZATION...........................................................
31
2.3.5.3 STATIC LOOP T ILI N G
............................................... 32
2.3.5.4 STATIC
SCHEDULING.................................................. 34
2.3.6 CODE G EN E RA TIO N
................................................................
37
3 SYMBOLIC PARALLELIZATION 41
3.1 SYMBOLIC T ILIN G
.................................................................................
42
3.1.1 DECOMPOSITION OF THE ITERATION S P A C E
............................... 43
3.1.2 EMBEDDING OF DATA
DEPENDENCIES..................................... 46
3.2 SYMBOLIC OUTER LOOP PARALLELIZATION
.............................................
50
3.2.1 TIGHT INTRA-TILE SCHEDULE VECTOR C A N D ID A TE S
..................
52
3.2.2 TIGHT INTER-TILE SCHEDULE
VECTORS........................................ 59
3.2.3 PARAMETRIC LATENCY FORM
ULA.............................................. 65
3.2.4 RUNTIME SCHEDULE S ELE CTIO N
..............................................
68
3.3 SYMBOLIC INNER LOOP
PARALLELIZATION............................................... 70
3.3.1 TIGHT INTRA-TILE SCHEDULE VECTORS
....................................
72
3.3.2 TIGHT INTER-TILE SCHEDULE VECTOR C A N D ID A TE S
................... 73
3.3.3 PARAMETRIC LATENCY FORM ULA
..............................................
77
3.3.4 RUNTIME SCHEDULE S E LE C TIO N
..............................................
79
3.4 RUNTIME SCHEDULE SELECTION ON INVASIVE T C P A S
......................... 81
3.5 EXPERIMENTAL R E SU
LTS.......................................................................
83
3.5.1 L A TE N C Y
................................................................................
84
3.5.2 I/O AND MEMORY D E M A N D
.................................................
86
3.5.3
SCALABILITY.............................................................................
90
3.6 RELATED W O R K
...................................................................................
92
3.7 S U M M A RY
.........................................................................................
96
4 SYMBOLIC MULTI-LEVEL PARALLELIZATION 99
4.1 SYMBOLIC HIERARCHICAL T ILIN G
........................................................... 100
4.1.1 DECOMPOSITION OF THE ITERATION S P A C E
...............................
101
4.1.2 EMBEDDING OF DATA DEPENDENCIES
.....................................
103
4.2 SYMBOLIC HIERARCHICAL S CHEDULING
.................................................
106
4.2.1 LATENCY-MINIMAL SEQUENTIAL SCHEDULE V E C TO R S
...............
107
4.2.2 TIGHT PARALLEL SCHEDULE V E C TO RS
........................................
112
4.2.3 PARAMETRIC LATENCY FORM ULA
..............................................
114
4.2.4 RUNTIME SCHEDULE S E LE C TIO N
..............................................
117
4.3 EXPERIMENTAL R ESU
LTS.......................................................................
117
4.3.1 L A TE N C Y
................................................................................
118
4.3.2 I/O AND MEMORY B A LA N CIN G
..............................................
121
4.3.3
SCALABILITY.............................................................................
122
4.4 RELATED W O R K
...................................................................................
123
4.5 S U M M A RY
..........................................................................................
125
5 ON-DEMAND FAULT-TOLERANT LOOP PROCESSING 127
5.1 FUNDAMENTALS AND FAULT M O D E L
....................................................
128
5.2 FAULT-TOLERANT LOOP E
XECUTION........................................................ 130
5.2.1 LOOP R
EPLICATION.................................................................
132
5.2.2 VOTING
INSERTION....................................................................
134
5.2.3 IMMEDIATE, EARLY, AND LATE V O TIN G
..................................
137
5.2.3.1 IMMEDIATE VOTING
..............................................
137
5.2.3.2 EARLY V O TIN G
.......................................................
141
5.2.3.3 LATE V O TIN G
........................................................... 143
5.3 VOTING FUNCTIONS IM PLEM ENTATION
.................................................
145
5.4 ADAPTIVE FAULT TOLERANCE THROUGH INVASIVE C O M P U TIN G
............
147
5.5 EXPERIMENTAL R ESU
LTS.......................................................................
151
5.5.1 LATENCY OVERHEAD
.............................................................. 151
5.5.2 AVERAGE ERROR DETECTION L A TE N C Y
.....................................
154
5.6 RELATED W O R K
...................................................................................
155
5.7 SUMMARY
........................................................................................
158
6 CONCLUSIONS AND OUTLOOK 159
6.1
CONCLUSIONS......................................................................................
159
6.2 O U TLO O K
............................................................................................
161
GERMAN PART 163
BIBLIOGRAPHY 169
AUTHOR*S OWN PUBLICATIONS 187
LIST OF SYMBOLS 191
ACRONYMS 195
|
any_adam_object | 1 |
author | Tanase, Alexandru-Petru |
author_facet | Tanase, Alexandru-Petru |
author_role | aut |
author_sort | Tanase, Alexandru-Petru |
author_variant | a p t apt |
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bvnumber | BV044546786 |
ctrlnum | (OCoLC)1008558192 (DE-599)DNB1141821346 |
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language | English |
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physical | ix, 196 Seiten Illustrationen, Diagramme 21 cm |
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spelling | Tanase, Alexandru-Petru Verfasser aut Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme vorgelegt von Alexandru-Petru Tanase aus Hermannstadt, Rumänien Symbolische Parallelisierung verschachtelter Schleifenprogramme Erlangen ; Nürnberg [2017] ix, 196 Seiten Illustrationen, Diagramme 21 cm txt rdacontent n rdamedia nc rdacarrier Dissertation Friedrich-Alexander-Universität Erlangen-Nürnberg 2017 Codegenerierung (DE-588)4010346-8 gnd rswk-swf Array Informatik (DE-588)4376624-9 gnd rswk-swf Feldrechner (DE-588)4016692-2 gnd rswk-swf Parallelrechner (DE-588)4173280-7 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Codegenerierung (DE-588)4010346-8 s Feldrechner (DE-588)4016692-2 s Parallelrechner (DE-588)4173280-7 s Array Informatik (DE-588)4376624-9 s DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029945732&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
spellingShingle | Tanase, Alexandru-Petru Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme Codegenerierung (DE-588)4010346-8 gnd Array Informatik (DE-588)4376624-9 gnd Feldrechner (DE-588)4016692-2 gnd Parallelrechner (DE-588)4173280-7 gnd |
subject_GND | (DE-588)4010346-8 (DE-588)4376624-9 (DE-588)4016692-2 (DE-588)4173280-7 (DE-588)4113937-9 |
title | Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme |
title_alt | Symbolische Parallelisierung verschachtelter Schleifenprogramme |
title_auth | Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme |
title_exact_search | Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme |
title_full | Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme vorgelegt von Alexandru-Petru Tanase aus Hermannstadt, Rumänien |
title_fullStr | Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme vorgelegt von Alexandru-Petru Tanase aus Hermannstadt, Rumänien |
title_full_unstemmed | Symbolic parallelization of nested loop programs = Symbolische Parallelisierung verschachtelter Schleifenprogramme vorgelegt von Alexandru-Petru Tanase aus Hermannstadt, Rumänien |
title_short | Symbolic parallelization of nested loop programs |
title_sort | symbolic parallelization of nested loop programs symbolische parallelisierung verschachtelter schleifenprogramme |
title_sub | = Symbolische Parallelisierung verschachtelter Schleifenprogramme |
topic | Codegenerierung (DE-588)4010346-8 gnd Array Informatik (DE-588)4376624-9 gnd Feldrechner (DE-588)4016692-2 gnd Parallelrechner (DE-588)4173280-7 gnd |
topic_facet | Codegenerierung Array Informatik Feldrechner Parallelrechner Hochschulschrift |
url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029945732&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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