A one-semester course in modeling of VLSI interconnections:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
New York, [New York] (222 East 46th Street, New York, NY 10017)
Momentum Press
2015
|
| Schriftenreihe: | Electronic circuits and semiconductor devices collection
|
| Schlagworte: | |
| Beschreibung: | Mode of access: World Wide Web. - System requirements: Adobe Acrobat reader Title from PDF title page (viewed on January 24, 2015) |
| Beschreibung: | xv, 340 Seiten Illustrationen, Diagramme |
| ISBN: | 9781606505120 |
Internformat
MARC
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| 100 | 1 | |a Goel, Ashok K. |4 aut | |
| 245 | 1 | 0 | |a A one-semester course in modeling of VLSI interconnections |c Ashok K. Goel |
| 264 | 1 | |a New York, [New York] (222 East 46th Street, New York, NY 10017) |b Momentum Press |c 2015 | |
| 300 | |a xv, 340 Seiten |b Illustrationen, Diagramme | ||
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| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 490 | 0 | |a Electronic circuits and semiconductor devices collection | |
| 500 | |a Mode of access: World Wide Web. - System requirements: Adobe Acrobat reader | ||
| 500 | |a Title from PDF title page (viewed on January 24, 2015) | ||
| 505 | 8 | |a Quantitative understanding of the parasitic capacitances and inductances and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. It is because more than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. An overview of the future interconnection technologies for the nanotechnology circuits will also be presented. This book will be the first book of its kind written for a one-semester course on the mathematical modeling of metallic interconnections on a VLSI circuit. In most institutions around the world offering BS, MS, and Ph.D. degrees in Electrical and Computer Engineering, such a course will be suitable for the first-year graduate students and it will also be appropriate as an elective course for senior level BS students. This book will also be of interest to practicing engineers in the field who are looking for a quick refresher on this subject | |
| 650 | 4 | |a Mathematisches Modell | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Mathematical models | |
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Datensatz im Suchindex
| _version_ | 1804177858843639808 |
|---|---|
| any_adam_object | |
| author | Goel, Ashok K. |
| author_facet | Goel, Ashok K. |
| author_role | aut |
| author_sort | Goel, Ashok K. |
| author_variant | a k g ak akg |
| building | Verbundindex |
| bvnumber | BV044517484 |
| classification_rvk | ZN 4952 |
| contents | Quantitative understanding of the parasitic capacitances and inductances and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. It is because more than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. An overview of the future interconnection technologies for the nanotechnology circuits will also be presented. This book will be the first book of its kind written for a one-semester course on the mathematical modeling of metallic interconnections on a VLSI circuit. In most institutions around the world offering BS, MS, and Ph.D. degrees in Electrical and Computer Engineering, such a course will be suitable for the first-year graduate students and it will also be appropriate as an elective course for senior level BS students. This book will also be of interest to practicing engineers in the field who are looking for a quick refresher on this subject |
| ctrlnum | (OCoLC)1011401478 (DE-599)BVBBV044517484 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Book |
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| id | DE-604.BV044517484 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T07:54:46Z |
| institution | BVB |
| isbn | 9781606505120 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029917088 |
| oclc_num | 1011401478 |
| open_access_boolean | |
| owner | DE-573 |
| owner_facet | DE-573 |
| physical | xv, 340 Seiten Illustrationen, Diagramme |
| publishDate | 2015 |
| publishDateSearch | 2015 |
| publishDateSort | 2015 |
| publisher | Momentum Press |
| record_format | marc |
| series2 | Electronic circuits and semiconductor devices collection |
| spelling | Goel, Ashok K. aut A one-semester course in modeling of VLSI interconnections Ashok K. Goel New York, [New York] (222 East 46th Street, New York, NY 10017) Momentum Press 2015 xv, 340 Seiten Illustrationen, Diagramme txt rdacontent n rdamedia nc rdacarrier Electronic circuits and semiconductor devices collection Mode of access: World Wide Web. - System requirements: Adobe Acrobat reader Title from PDF title page (viewed on January 24, 2015) Quantitative understanding of the parasitic capacitances and inductances and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. It is because more than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. An overview of the future interconnection technologies for the nanotechnology circuits will also be presented. This book will be the first book of its kind written for a one-semester course on the mathematical modeling of metallic interconnections on a VLSI circuit. In most institutions around the world offering BS, MS, and Ph.D. degrees in Electrical and Computer Engineering, such a course will be suitable for the first-year graduate students and it will also be appropriate as an elective course for senior level BS students. This book will also be of interest to practicing engineers in the field who are looking for a quick refresher on this subject Mathematisches Modell Integrated circuits Very large scale integration Mathematical models VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s DE-604 Erscheint auch als Online-Ausgabe 978-1-60650-513-7 |
| spellingShingle | Goel, Ashok K. A one-semester course in modeling of VLSI interconnections Quantitative understanding of the parasitic capacitances and inductances and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. It is because more than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. An overview of the future interconnection technologies for the nanotechnology circuits will also be presented. This book will be the first book of its kind written for a one-semester course on the mathematical modeling of metallic interconnections on a VLSI circuit. In most institutions around the world offering BS, MS, and Ph.D. degrees in Electrical and Computer Engineering, such a course will be suitable for the first-year graduate students and it will also be appropriate as an elective course for senior level BS students. This book will also be of interest to practicing engineers in the field who are looking for a quick refresher on this subject Mathematisches Modell Integrated circuits Very large scale integration Mathematical models VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4117388-0 |
| title | A one-semester course in modeling of VLSI interconnections |
| title_auth | A one-semester course in modeling of VLSI interconnections |
| title_exact_search | A one-semester course in modeling of VLSI interconnections |
| title_full | A one-semester course in modeling of VLSI interconnections Ashok K. Goel |
| title_fullStr | A one-semester course in modeling of VLSI interconnections Ashok K. Goel |
| title_full_unstemmed | A one-semester course in modeling of VLSI interconnections Ashok K. Goel |
| title_short | A one-semester course in modeling of VLSI interconnections |
| title_sort | a one semester course in modeling of vlsi interconnections |
| topic | Mathematisches Modell Integrated circuits Very large scale integration Mathematical models VLSI (DE-588)4117388-0 gnd |
| topic_facet | Mathematisches Modell Integrated circuits Very large scale integration Mathematical models VLSI |
| work_keys_str_mv | AT goelashokk aonesemestercourseinmodelingofvlsiinterconnections |