Verfügbarkeit: Dataflow-based parallel signal processing and classification on reconfigurable hardware

Dataflow-based parallel signal processing and classification on reconfigurable hardware:

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Bibliographische Detailangaben
1. Verfasser:	Wöhrle, Hendrik (VerfasserIn)
Format:	Abschlussarbeit Buch
Sprache:	English
Veröffentlicht:	Bremen 2017
Schlagworte:	Hochschulschrift
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	vi, 287 Seiten Illustrationen, Diagramme

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MARC


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Datensatz im Suchindex

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adam_text	CONTENTS PREFACE I ABSTRACT I DEUTSCHE ZUSAMMENFASSUNG II ACKNOWLEDGEMENTS III 1 THESIS MOTIVATION AND OVERVIEW 1 1.1 M OTIVATION..................................................................................................... 1 1.2 OBJECTIVES OF THE THESIS.................................................................................. 4 1.3 STRUCTURE OF THE T H E S IS .................................................................................. 4 1.4 CONTRIBUTIONS................................................................................................ 9 1 FOUNDATIONS AND BACKGROUND 11 2 CURRENT PROBLEMS IN DATA SCIENCE 13 2.1 CHALLENGES IN BIG DATA ANALYTICS ................................................................. 13 2.2 EXAMPLE APPLICATION: REAL-TIME ANALYTICS OF PHYSIOLOGICAL D A T A .............. 21 2.3 CHAPTER SUMMARY AND D ISCUSSION............................................................... 29 3 THEORETICAL AND TECHNICAL BACKGROUND 31 3.1 PARALLEL COM PUTING....................................................................................... 33 3.2 DATAFLOW MODELS AND ARCHITECTURES ............................................................ 43 3.3 RECONFIGURABLE COMPUTING AND FIELD PROGRAMMABLE GATE A RRAY S .............. 57 3.4 CHAPTER SUMMARY AND D ISCUSSION............................................................... 69 II SYSTEM ARCHITECTURE 71 4 DATAFLOW HARDWARE ACCELERATOR ARCHITECTURE 73 4.1 MAPPING DATAFLOW MODELS TO HARDWARE....................................................... 74 4.2 THE HETEROGENEOUS DATAFLOW ARCHITECTURE ................................................. 95 4.3 CAEMO: A SYSTOLIC ACCELERATOR FOR MATRIX OPERATIONS .............................. 105 4.4 CHAPTER SUMMARY AND D ISCUSSION..................................................................116 5 MACHINE LEARNING ALGORITHM DESIGN FOR DATAFLOW ARCHITECTURES 119 5.1 BASIC DEFINITIONS AND TERMINOLOGY..................................................................120 5.2 MACHINE LEARNING FOR DATA STREAMS ............................................................... 122 5.3 ONLINE DIMENSIONALITY REDUCTION .................................................................... 127 5.4 CHAPTER SUMMARY AND D ISCUSSION..................................................................132 CHAPTER CONTENTS 6 SOFTWARE ARCHITECTURE AND DEVELOPMENT TOOLS 133 6.1 DESIGN ENVIRONM ENT........................................................................................ 134 6.2 ACTOR DEFINITION BY THE RESPACE ACTOR L AN G U A G E ..........................................139 6.3 DESIGN SYNTHESIS AND IMPLEMENTATION.............................................................145 6.4 RUNTIME E NVIRONM ENT..................................................................................... 146 6.5 VERIFICATION OF DATAFLOW HARDWARE ACCELERATORS ............................................ 150 6.6 CHAPTER SUMMARY AND D ISCUSSION.................................................................. 152 III EVALUATION AND APPLICATIONS 153 7 ANALYSIS OF BASIC BUILDING BLOCKS AND ALGORITHMS 155 7.1 EVALUATION PLATFORM S........................................................................................ 155 7.2 EVALUATION CRITERIA AND M ETHODOLOGY.............................................................159 7.3 BASELINE POWER CONSUMPTION OF THE ZYNQBRAIN...............................................161 7.4 DATA TRANSFER PERFORMANCE................................................................................162 7.5 COMPUTING PERFORMANCE: DATA STREAM OPERATIONS ......................................... 166 7.6 COMPUTING PERFORMANCE: FINITE IMPULSE RESPONSE F ILTE R...............................168 7.7 COMPUTING PERFORMANCE: LARGE-SCALE MATRIX MULTIPLICATION ......................... 170 7.8 MACHINE LEARNING FOR DATA WITH CONCEPT DRIFT AND CHANGE.............................184 7.9 CHAPTER SUMMARY AND D ISCUSSION.................................................................. 191 8 CASE STUDIES - REAL-TIME PROCESSING OF PHYSIOLOGICAL DATA 193 8.1 HYBRID AND MULTIMODAL ONLINE MOVEMENT PREDICTION .................................... 194 8.2 ONLINE ADAPTATION FOR THE DETECTION OF EVENT RELATED POTENTIALS ................... 216 8.3 CHAPTER SUMMARY AND D ISCUSSION.................................................................. 230 IV CONCLUSIONS 231 9 THESIS SUMMARY AND FUTURE ASPECTS 233 9.1 SUMMARY........................................................................................................... 233 9.2 LIMITATIONS OF THE A PPROACH.............................................................................235 9.3 FUTURE W O RK ..................................................................................................... 236 APPENDIX 243 AUTHOR*S PUBLICATIONS 243 GLOSSARY 247 LIST OF SYMBOLS 251 LIST OF FIGURES 253 LIST OF TABLES 257 BIBLIOGRAPHY 259
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spelling	Wöhrle, Hendrik Verfasser (DE-588)1143543580 aut Dataflow-based parallel signal processing and classification on reconfigurable hardware von Hendrik Wöhrle Bremen 2017 vi, 287 Seiten Illustrationen, Diagramme txt rdacontent n rdamedia nc rdacarrier Dissertation Universität Bremen 2017 (DE-588)4113937-9 Hochschulschrift gnd-content Universität Bremen (DE-588)2001386-3 dgg DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029891366&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Wöhrle, Hendrik Dataflow-based parallel signal processing and classification on reconfigurable hardware
subject_GND	(DE-588)4113937-9
title	Dataflow-based parallel signal processing and classification on reconfigurable hardware
title_auth	Dataflow-based parallel signal processing and classification on reconfigurable hardware
title_exact_search	Dataflow-based parallel signal processing and classification on reconfigurable hardware
title_full	Dataflow-based parallel signal processing and classification on reconfigurable hardware von Hendrik Wöhrle
title_fullStr	Dataflow-based parallel signal processing and classification on reconfigurable hardware von Hendrik Wöhrle
title_full_unstemmed	Dataflow-based parallel signal processing and classification on reconfigurable hardware von Hendrik Wöhrle
title_short	Dataflow-based parallel signal processing and classification on reconfigurable hardware
title_sort	dataflow based parallel signal processing and classification on reconfigurable hardware
topic_facet	Hochschulschrift
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029891366&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
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