Verfügbarkeit: Birthing the computer

Birthing the computer: from drums to cores

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Bibliographische Detailangaben
1. Verfasser:	Kaisler, Stephen Hendrick (VerfasserIn)
Format:	Buch
Sprache:	English
Veröffentlicht:	Newcastle upon Tyne, UK Cambridge Scholars Publishing [2017]
Schlagworte:	Geschichte Computerarchitektur Computer architecture / History
Online-Zugang:	Inhaltsverzeichnis
Beschreibung:	xxii, 345 Seiten Illustrationen 22 cm
ISBN:	9781443885119 1443885118

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Datensatz im Suchindex

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adam_text	TABLE OF CONTENTS LIST OF FIGURES ........................................................................................... XVI LIST OF TABLES ............................................................................................ XIX ACKNOWLEDGEMENT .................................................................................. XXIII INTRODUCTION ............................................................................................ XXIV PART I: MAGNETIC DRUM MACHINES ............................................................ 1 CHAPTER ONE ................................................................................................. 3 IBM 650 MAGNETIC DRUM CALCULATOR 1.1 650 SYSTEM ARCHITECTURE .................................................................. 4 1.1.1 MAGNETIC DRUM MEMORY ......................................................... 5 1.1.2 ARITHMETIC UNIT ....................................................................... 7 1.1.3 IBM 650 SELF-CHECKING .......................................................... 8 1.1.4 IBM 650 CONSOLE .................................................................. 10 1.1.5 MAGNETIC TAPE UNITS ............................................................. 11 1.1.6 IBM 652 CONTROL UNIT ........................................................... 11 1.1.7 IBM 653 HIGH-SPEED CORE STORAGE UNIT .............................. 11 1.1.8 IBM 407 ACCOUNTING MACHINE .............................................. 12 1.2 IBM 650 INSTRUCTION SET ................................................................. 12 1.2.1 I/O INSTRUCTIONS ...................................................................... 13 1.2.2 ARITHMETIC INSTRUCTIONS .......................................................... 13 1.2.3 SHIFTING INSTRUCTIONS .............................................................. 15 1.2.4 BRANCHING INSTRUCTIONS .......................................................... 15 1.2.5 TABLE LOOKUP INSTRUCTION ...................................................... 16 1.2.6 MISCELLANEOUS INSTRUCTIONS .................................................... 16 1.2.7 INDEX ACCUMULATOR INSTRUCTIONS ............................................ 17 1.2.8 INDEX ACCUMULATOR OPERATIONS INSTRUCTIONS .......................... 17 1.2.9 FLOATING POINT INSTRUCTIONS .................................................... 18 1.2.10 IAS INSTRUCTION .................................................................... 19 1.3 IBM 650 PROGRAMMING .................................................................. 20 1.4 SYMBOLIC ASSEMBLY ....................................................................... 21 1.5 IBM 650 RAMAC ......................................................................... 22 1.6 IBM 650 ASSESSMENT ..................................................................... 23 $ B1IOTHEK DEUTSCHES MUSEUM HLUENCHE A VIII TABLE OF CONTENTS CHAPTER TWO .............................................................................................. 25 ROYAL MCBEE/LIBRASCOPE MACHINES 2.1 LGP-30 SYSTEM ARCHITECTURE ......................................................... 27 2.2 LGP-30 INSTRUCTION SET .................................................................. 28 2.3 THE STORY OF MEL ............................................................................ 30 2.4 LGP-30 ASSESSMENT ....................................................................... 34 2.5 THE LGP-21 ................................................................................... 34 2.5.1 LGP-21 SYSTEM ..................................................................... 35 2.5.2 LGP-21 MEMORY ................................................................... 36 2.5.3 LGP-21 CONTROL REGISTERS ..................................................... 37 2.6 LGP-21 INSTRUCTION SET .................................................................. 39 2.7 TIMING AND OPTIMIZATION ............................................................... 41 2.8 LGP-21 ASSESSMENT ....................................................................... 41 CHAPTER THREE ............................................................................................ 44 BENDIX G MACHINES 3.1 BENDIX G-15 ................................................................................... 44 3.2 G-15 SYSTEM CONFIGURATION ........................................................... 50 3.2.1 SHORT LINES ............................................................................ 51 3.2.2 REGISTERS ................................................................................ 51 3.2.3 COMMAND LINES .....................; .............................................. 52 3.2.4 I/O SYSTEM ............................................................................. 52 3.3 G-15 INSTRUCTION SET ....................................................................... 53 3.3.1 SPECIAL VALUES FOR S/D FIELDS ................................................ 54 3.3.2 SPECIAL INSTRUCTIONS ............................................................... 54 3.4 PERIPHERAL DEVICES ......................................................................... 56 3.4.1 MAGNETIC TAPE MTA-2 .......................................................... 56 3.4.2 DIGITAL DIFFERENTIAL ANALYZER DA-1 ....................................... 57 3.4.3 GRAPH PLOTTER PA-3 ................................................................ 57 3.4.4 PUNCHED CARD COUPLER CA-1/CA-2 ....................................... 57 3.4.5 UNIVERSAL CODE ACCESSORY AN-1 .......................................... 58 3.5 PROGRAMMING LANGUAGES ............................................................... 58 3.5.1 ALGO .................................................................................... 58 3.5.2 INTERCOM 1000 ....................................................................... 61 3.5.3 SAMPLE G-15 PROGRAM ........................................................... 66 3.6 TRACKING STATION APPLICATION ......................................................... 67 3.7 G-15 ASSESSMENT ........................................................................... 68 FURTHER READING ......................................................................................... 69 EXERCISES FOR THE READER ............................................................................ 70 BIRTHING THE COMPUTER: FROM DRUMS TO CORES IX PART II: CORE MEMORY MACHINES ............................................................ 73 CHAPTER FOUR .............................................................................................. 77 RCA BIZMAC I/II 4.1 BIZMAC SYSTEM ARCHITECTURE ...................................................... 81 4.2 BIZMAC I/O SYSTEM ..................................................................... 83 4.3 DATA REPRESENTATION ....................................................................... 84 4.4 BIZMAC INSTRUCTION SET ................................................................ 84 4.5 BIZMAC ASSESSMENT .................................................................... 85 CHAPTER FIVE .............................................................................................. 86 FERRANTI ATLAS 5.1 ATLAS SYSTEM ARCHITECTURE ............................................................. 89 5.1.1 CENTRAL PROCESSOR ................................................................... 89 5.1.2 PROGRAM CONTROL .................................................................... 90 5.1.3 STORAGE HIERARCHY .................................................................. 91 5.1.4 VIRTUAL STORAGE ...................................................................... 92 5.2 PERIPHERALS ..................................................................................... 94 5.3 ATLAS INSTRUCTION SET .............. ........ 94 5.3.1 FLOATING POINT ARITHMETIC INSTRUCTIONS .................................. 96 5.3.2 INDEXING OPERATIONS .............................................................. 97 5.3.3 ATLAS BRANCHING INSTRUCTIONS ................................................. 98 5.3.4 ATLAS SHIFTING INSTRUCTIONS ..................................................... 99 5.3.5 ATLAS ODD/EVEN TEST INSTRUCTIONS ........................................... 99 5.3.6 ATLAS B-TEST REGISTER INSTRUCTIONS ........................................ 100 5.3.7 ATLAS INSTRUCTION EXAMPLE ................................................... 100 5.4 ATLAS PROGRAMMING ...................................................................... 101 5.5 THE ATLAS SUPERVISOR .................................................................... 102 5.5.1 STRUCTURE OF THE ATLAS SUPERVISOR ........................................ 103 5.5.2 JOB STRUCTURE ........................................................................ 105 5.5.3 PROGRAMS ............................................................................. 106 5.5.4 PROCESS CONTROL ................................................................... 106 5.5.5 INTERRUPT HANDLING ............................................................... 107 5.5.6 ATLAS SUPERVISOR ASSESSMENT .............................................. 108 5.6 ATLAS 2 .......................................................................................... 108 5.6.1 ATLAS 2 CENTRAL PROCESSOR .................................................... 109 5.6.2 ATLAS 2 MEMORY ................................................................... 110 5.6.3 MAGNETIC TAPE ..................................................................... 112 5.6.4 MAGNETIC DISC FILES ............................................................. 113 5.7 THE ATLAS 2 SUPERVISOR ................................................................. 113 5.7.1 INTERRUPT ROUTINES ................................................................ 114 X TABLE OF CONTENTS 5.7.2 SUPERVISOR EXTRACODE ROUTINES ........................................... 115 5.7.3 EXTENDED INTERRUPT ROUTINES ................................................ 116 5.7.4 OBJECT PROGRAMS ................................................................. 116 5.7.5 ERROR CONDITIONS .................................................................. 117 5.8 ATLAS ASSESSMENT ......................................................................... 117 CHAPTER SIX .............................................................................................. 120 JOHNNIAC 6.1 JOHNNIAC SYSTEM ARCHITECTURE ................................................ 122 6.2 JOHNNIAC SYSTEM CONFIGURATION ............................................. 123 6.3 JOHNNIAC INSTRUCTION SET ......................................................... 124 6.3.1 CONDITIONAL TRANSFER ORDERS ................................................ 124 6.3.2 TRANSFER ORDERS ................................................................... 125 6.3.3 ADD ORDERS .......................................................................... 126 6.3.4 MULTIPLY OPERATIONS ............................................................ 127 6.3.5 DIVISION ORDERS ................................................................... 129 6.3.6 STORE ORDERS ......................................................................... 130 6.3.7 REGISTER MOVEMENT ORDERS ................................................. 130 6.3.8 SHIFT ORDERS ......................................................................... 131 6.3.9 INPUT/OUTPUT ORDERS ............................................................ 132 6.3.10 DRUM ORDERS ....................................................................... 133 6.3.11 LOGICAL PRODUCT ORDERS ..................................................... 134 6.3.12 CONTROL ORDERS ................................................................... 134 6.4 JOHNNIAC OPERATION ................................................................. 135 6.5 JOSS ............................................................................................ 136 6.5.1 JOSS STRUCTURE .................................................................... 137 6.5.2 JOSS REMOTE CONSOLE ......................................................... 138 6.5.3 JOSS IMPLEMENTATION .......................................................... 139 6.6 JOHNNIAC ASSESSMENT .............................................................. 140 FURTHER READING ....................................................................................... 141 EXERCISES FOR THE READER .......................................................................... 143 PART III: TRANSISTOR MACHINES .............................................................. 145 CHAPTER SEVEN .......................................................................................... 147 UNIVAC SOLID STATE COMPUTER 7.1 SOLID STATE COMPUTER ARCHITECTURE .............................................. 148 7.1.1 SSC CENTRAL PROCESSOR ......................................................... 152 7.1.2 MAGNETIC DRUM ................................................................... 153 BIRTHING THE COMPUTER: FROM DRUMS TO CORES XI 7.1.3 OPERATOR S CONSOLE .............................................................. 154 7.2 SSC80/SSC90 INSTRUCTIONS .......................................................... 155 7.2.1 EXECUTING AN INSTRUCTION ...................................................... 156 7.2.2 ARITHMETIC INSTRUCTIONS ........................................................ 156 7.2.3 TRANSFER INSTRUCTIONS ............................................................ 156 7.2.4 LOGICAL AND SHIFT INSTRUCTIONS ............................................. 157 7.2.5 COMPARISON INSTRUCTIONS ...................................................... 157 7.2.6 TRANSLATE INSTRUCTIONS .......................................................... 158 7.2.7 SS80 PRINTER CONTROL INSTRUCTIONS ........................................ 158 7.2.8 CARD READER CONTROL INSTRUCTIONS ........................................ 158 7.3 SSC PERIPHERALS ........................................................................... 159 7.4 SOLID STATE COMPUTER SYSTEM SOFTWARE ....................................... 160 7.4.1 FLOW-MATIC ................................................................... 160 7.5 SSC ASSESSMENT .......................................................................... 161 CHAPTER EIGHT ........................................................................................... 162 UNIVAC 418 8.1 UNIVAC 418-I ............................................................................ 163 8.2 UNIVAC 418 SYSTEM ARCHITECTURE ............................................. 163 8.3 INSTRUCTION FORMAT ........................................................................ 163 8.3.1 TYPE I INSTRUCTIONS .............................................................. 164 8.3.2 TYPE II INSTRUCTIONS ............................................................. 164 8.3.3 TYPE III INSTRUCTIONS ............................................................ 165 8.4 SYSTEM SOFTWARE .......................................................................... 165 8.5 UNIVAC 418-II ........................................................................... 165 8.6 UNIVAC 418-III .......................................................................... 166 8.6.1 UNIVAC 418-III SYSTEM ARCHITECTURE ................................ 167 8.6.2 COMMAND/ARITHMETIC UNIT (CAU) ...................................... 168 8.6.3 MAIN STORAGE ....................................................................... 169 8.6.4 I/O MODULES (IOMS) ............................................................ 170 8.6.5 MAGNETIC DRUMS .................................................................. 173 8.6.6 ATTACHED PROCESSORS ............................................................ 174 8.6.7 COMMUNICATIONS SYSTEMS ................................................... 174 8.6.8 UNIT RECORD PERIPHERALS ...................................................... 175 8.7 UNIVAC 418 SYSTEM SOFTWARE ................................................... 175 8.7.1 RTOS EXECUTIVE .................................................................. 176 8.7.2 PROGRAMMING LANGUAGES ..................................................... 181 8.7.3 SYSTEM APPLICATIONS ............................................................ 182 8.8 UNIVAC 418-111 APPLICATION ...................................................... 183 8.8 UNIVAC 418 ASSESSMENT ........................................................... 183 XII TABLE OF CONTENTS CHAPTER NINE ............................................................................................ 185 UNIVAC 490/494 9.1 UNIVAC 494 ............................................................................... 187 9.1 SYSTEM ARCHITECTURE ..................................................................... 188 9.1.1 CENTRAL PROCESSOR ................................................................. 189 9.1.2 MEMORY ............................................................................... 191 9.1.3 1/0 SYSTEM ........................................................................... 191 9.1.4 COMMUNICATIONS HANDLING .................................................. 193 9.1.5 TRANSFER SWITCH ................................................................... 194 9.2 INSTRUCTION SET .............................................................................. 195 9.2.1 SHIFT INSTRUCTIONS ................................................................. 197 9.2.2 UNIVAC 494 TRANSFER INSTRUCTIONS .................................... 199 9.2.3 ARITHMETIC INSTRUCTIONS ........................................................ 201 9.3.4 LOGICAL INSTRUCTIONS ............................................................. 203 9.3.5 COMPARISON INSTRUCTIONS ...................................................... 204 9.3.6 JUMP INSTRUCTIONS ................................................................ 205 9.3.7 SEQUENCE MODIFYING INSTRUCTIONS ........................................ 206 9.3.8 1/0 INSTRUCTIONS .................................................................... 207 9.3 PERIPHERALS ................................................................................... 208 9.3.1 MAGNETIC DRUMS .................................................................. 209 9.3.2 MAGNETIC TAPE SUBSYSTEM ....:.............................................. 210 9.3.3 OPERATOR S CONSOLE .............................................................. 210 9.3.4 HIGH-SPEED PRINTER SUBSYSTEM ............................................ 210 9.4 UNIVAC 490/494 SYSTEM SOFTWARE ............................................ 211 9.4.1 PRIMARY INPUT STREAM .......................................................... 211 9.4.2 INPUT COOPERATIVE ................................................................ 211 9.4.3 PROGRAMMING LANGUAGES ..................................................... 212 9.5 UNIVAC 490/494 ASSESSMENT .................................................... 212 CHAPTER TEN ............................................................................................. 214 MIT S TX-0 10.1 TX-0 SYSTEM ARCHITECTURE ......................................................... 217 10.1.1 TX-0 REGISTERS .................................................................. 217 10.1.2 TOGGLE SWITCH STORAGE ...................................................... 218 10.1.3 MAIN MEMORY .................................................................... 218 10.2 TX-0 INSTRUCTIONS ....................................................................... 218 10.2.1 TX-0 OPERATE INSTRUCTIONS ................................................. 219 10.2.2 COMBINING INSTRUCTIONS ..................................................... 220 10.2.3 MODIFIED INSTRUCTION SET .................................................... 222 10.3 OPERATING MODES ........................................................................ 223 10.4 TX-0 I/O EQUIPMENT .................................................................. 224 BIRTHING THE COMPUTER: FROM DRUMS TO CORES XIII 10.5 FLIT ........................................................................................... 224 10.6 TX-1 ........................................................................................... 225 10.7 TX-2 ........................................................................................... 225 10.7.1 TX-2 SYSTEM ARCHITECTURE ................................................. 226 10.8 TX-0 AND TX-2 ASSESSMENT ....................................................... 227 CHAPTER ELEVEN ........................................................................................ 229 PHILCO FORD COMPUTERS 11.1 PHILCO 1000 ................................................................................ 230 11.1.1 PHILCO 1000 CENTRAL PROCESSOR ........................................... 231 11.1.2 PHILCO 1000 SYSTEM ARCHITECTURE ...................................... 232 11.1.3 INSTRUCTION SET ................................................................... 232 11.2 PHILCO TRANSAC S-2000 ......................................................... 233 11.3 TRANSAC S-2000 SYSTEM ARCHITECTURE ................................... 238 11.3.1 SECONDARY MEMORY ........................................................... 239 11.4 TRANSAC S-2000 INSTRUCTION SET ............................................ 240 11.4.1 PROGRAM CONTROL ................................................................ 241 11.4.2 INSTRUCTION CONTROL ............................................................ 241 11.4.3 ALGORITHM CONTROL ............................................................. 241 11.4.4 FLOATING POINT CONTROL ....................................................... 242 11.4.5 MEMORY CYCLE CONTROL ...................................................... 242 11.5 PHILCO 212 .................................................................................. 242 11.5.1 CONTROL UNIT ....................................................................... 245 11.5.2 INSTRUCTION UNIT ................................................................. 245 11.5.3 INDEX UNIT .......................................................................... 246 11.5.4 ARITHMETIC UNIT ................................................................. 247 11.5.5 STORE UNIT .......................................................................... 248 11.5.6 I/O SUBSYSTEM ................................................................... 248 11.5.7 REAL-TIME SYSTEM ............................................................. 249 11.5.8 PHILCO 212 INSTRUCTION SET ................................................. 250 11.6 OPERATING SYSTEM 32KSYS ........................................................ 265 11.7 TRANSAC S-2000 SOFTWARE ..................................................... 266 11.8 PHILCO 2400 INPUT/OUTPUT SYSTEM .............................................. 269 11.8.1 PHILCO 2400 SYSTEM ARCHITECTURE ...................................... 270 11.8.2 EXECUTIVE CONTROL .............................................................. 271 11.8.3 PROGRAM CONTROL ................................................................ 272 11.8.4 ARITHMETIC ELEMENT ........................................................... 273 11.8.5 MAIN MEMORY .................................................................... 273 11.8.6 OPERATOR CONTROL PANEL ...................................................... 274 11.8.7 PHILCO 2400 INSTRUCTION SET ............................................... 275 11.8.8 I/O OPERATIONS ................................................................... 275 XIV TABLE OF CONTENTS 11.8.9 INTERNAL OPERATIONS ............................................................ 279 11.8.10 ARITHMETIC OPERATIONS ..................................................... 284 11.8.11 PHILCO 2400 I/O DEVICES .................................................. 287 11.9 ASSESSMENT OF THE PHILCO MACHINES ........................................... 287 CHAPTER TWELVE ....................................................................................... 289 BENDIX G-20 12.1 BENDIX G-20 SYSTEM ARCHITECTURE ............................................. 289 12.1.1 ARITHMETIC UNIT ................................................................. 292 12.1.2 REGISTERS ............................................................................ 292 12.1.3 CORE MEMORY .................................................................... 293 12.1.4 INTERRUPTS ........................................................................... 293 12.2 INSTRUCTION SET ARCHITECTURE ....................................................... 294 12.2.1 ADD/SUBTRACT OPERATIONS AND TESTS ................................... 294 12.2.2 LOGIC OPERATIONS AND TESTS ............................................... 296 12.2.3 REPEATED COMMANDS ......................................................... 297 12.2.4 MULTIPLY/DIVIDE ................................................................. 298 12.2.5 STORAGE OPERATIONS ............................................................ 298 12.2.6 INDEX OPERATIONS ............................................................... 299 12.2.7 CONTROL OPERATIONS ............................................................ 299 12.2.81/0 OPERATIONS ................................................................... 300 12.2.9 BUS REGISTER OPERATIONS .................................................... 301 12.3 I/O SYSTEM ................................................................................. 302 12.4 G-21 DUAL PROCESSOR .................................................................. 302 12.4.1 G-21 SOFTWARE ................................................................... 303 12.5 BENDIX G-20 ASSESSMENT ........................................................... 303 CHAPTER THIRTEEN ...................................................................................... 304 PACKARD BELL 13.1 PB250 SYSTEM ARCHITECTURE ....................................................... 306 13.1.1 CENTRAL PROCESSOR ............................................................... 307 13.1.2 MAIN MEMORY .................................................................... 308 13.1.3 FLEXOWRITER ........................................................................ 309 13.1.4 OTHER I/O DEVICES .............................................................. 310 13.1.5 HYCOMP 250 ................................................................... 310 13.2 PB250 COMMANDS ..................................................................... 311 13.2.1 CLASS I COMMANDS ............................................................. 312 13.2.2 CLASS II COMMANDS ........................................................... 314 13.2.3 CLASS III COMMANDS .......................................................... 316 13.2.4 CLASS IV COMMANDS .......................................................... 316 13.2.5 SEQUENCE TAG .................................................................... 317 BIRTHING THE COMPUTER: FROM DRUMS TO CORES XV 13.3 PACKARD BELL 440 ........................................................................ 318 13.3.1 PB440 SYSTEM ARCHITECTURE .............................................. 321 13.3.2 MEMORY SYSTEM ................................................................ 322 13.3.3 I/O SYSTEM ......................................................................... 323 13.3.4 PB440 PROGRAMMING ......................................................... 324 13.4 PB440 MICRO INSTRUCTION FORMAT ............................................... 325 13.5 PACKARD BELL ASSESSMENT ........................................................... 325 FURTHER READING ....................................................................................... 327 EXERCISES FOR THE READER .......................................................................... 328 APPENDIX A: GLOSSARY ............................................................................. 331 REFERENCES ............................................................................................... 332 INDEX ........................................................................................................ 340
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publisher	Cambridge Scholars Publishing
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spelling	Kaisler, Stephen Hendrick Verfasser aut Birthing the computer from drums to cores by Stephen H. Kaisler Newcastle upon Tyne, UK Cambridge Scholars Publishing [2017] © 2017 xxii, 345 Seiten Illustrationen 22 cm txt rdacontent n rdamedia nc rdacarrier Geschichte gnd rswk-swf Geschichte Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Computer architecture / History Computerarchitektur (DE-588)4048717-9 s Geschichte z DE-604 Digitalisierung Deutsches Museum application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029824896&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis
spellingShingle	Kaisler, Stephen Hendrick Birthing the computer from drums to cores Geschichte Computerarchitektur (DE-588)4048717-9 gnd
subject_GND	(DE-588)4048717-9
title	Birthing the computer from drums to cores
title_auth	Birthing the computer from drums to cores
title_exact_search	Birthing the computer from drums to cores
title_full	Birthing the computer from drums to cores by Stephen H. Kaisler
title_fullStr	Birthing the computer from drums to cores by Stephen H. Kaisler
title_full_unstemmed	Birthing the computer from drums to cores by Stephen H. Kaisler
title_short	Birthing the computer
title_sort	birthing the computer from drums to cores
title_sub	from drums to cores
topic	Geschichte Computerarchitektur (DE-588)4048717-9 gnd
topic_facet	Geschichte Computerarchitektur
url	http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=029824896&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT kaislerstephenhendrick birthingthecomputerfromdrumstocores

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