APA (7th ed.) Citation

Liebmann, L. W., & Vaidyanathan, K. (2015). Design technology co-optimization in the era of sub-resolution IC scaling. SPIE. https://doi.org/10.1117/3.2217861

Chicago Style (17th ed.) Citation

Liebmann, Lars W., and Kaushik Vaidyanathan. Design Technology Co-optimization in the Era of Sub-resolution IC Scaling. Bellingham, Washington: SPIE, 2015. https://doi.org/10.1117/3.2217861.

MLA (9th ed.) Citation

Liebmann, Lars W., and Kaushik Vaidyanathan. Design Technology Co-optimization in the Era of Sub-resolution IC Scaling. SPIE, 2015. https://doi.org/10.1117/3.2217861.