Design technology co-optimization in the era of sub-resolution IC scaling:
Tackle the challenges facing the most advanced technology nodes in the microelectronics industry with the help of design technology co-optimization (DTCO). This mediation process aims to ensure competitive technology architecture definition while avoiding schedule or yield risks caused by unrealisti...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Bellingham, Washington
SPIE
[2015]
|
| Schriftenreihe: | Tutorial texts in optical engineering
volume TT104 |
| Schlagworte: | |
| Online-Zugang: | FHD01 Volltext |
| Zusammenfassung: | Tackle the challenges facing the most advanced technology nodes in the microelectronics industry with the help of design technology co-optimization (DTCO). This mediation process aims to ensure competitive technology architecture definition while avoiding schedule or yield risks caused by unrealistically aggressive process assumptions. Find the answers in this Tutorial Text, which reviews the fundamental design objectives as well as the resulting topological constraints of a standard cell logic design flow; cell design, placement, and routing are examined against the backdrop of ever-increasing design constraints in advanced technology nodes |
| Beschreibung: | 1 online resource (160 pages) |
| ISBN: | 9781628416695 |
| DOI: | 10.1117/3.2217861 |
Internformat
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Datensatz im Suchindex
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| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1117/3.2217861 |
| format | Electronic eBook |
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| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:47:32Z |
| institution | BVB |
| isbn | 9781628416695 |
| language | English |
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| physical | 1 online resource (160 pages) |
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| publishDate | 2015 |
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| publisher | SPIE |
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| series | Tutorial texts in optical engineering |
| series2 | Tutorial texts in optical engineering SPIE Digital Library |
| spelling | Liebmann, Lars W. Verfasser aut Design technology co-optimization in the era of sub-resolution IC scaling Lars Liebmann, Kaushik Vaidyanathan, and Lawrence Pileggi Bellingham, Washington SPIE [2015] 1 online resource (160 pages) txt rdacontent c rdamedia cr rdacarrier Tutorial texts in optical engineering volume TT104 SPIE Digital Library Tackle the challenges facing the most advanced technology nodes in the microelectronics industry with the help of design technology co-optimization (DTCO). This mediation process aims to ensure competitive technology architecture definition while avoiding schedule or yield risks caused by unrealistically aggressive process assumptions. Find the answers in this Tutorial Text, which reviews the fundamental design objectives as well as the resulting topological constraints of a standard cell logic design flow; cell design, placement, and routing are examined against the backdrop of ever-increasing design constraints in advanced technology nodes Integrated circuits / Design and construction Lithography, Electron beam Electronic books Vaidyanathan, Kaushik Verfasser aut Pileggi, Lawrence 1962- Sonstige oth Erscheint auch als Druck-Ausgabe 1-6284-1905-9 Tutorial texts in optical engineering volume TT104 (DE-604)BV044913200 104 https://doi.org/10.1117/3.2217861 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Liebmann, Lars W. Vaidyanathan, Kaushik Design technology co-optimization in the era of sub-resolution IC scaling Tutorial texts in optical engineering Integrated circuits / Design and construction Lithography, Electron beam |
| title | Design technology co-optimization in the era of sub-resolution IC scaling |
| title_auth | Design technology co-optimization in the era of sub-resolution IC scaling |
| title_exact_search | Design technology co-optimization in the era of sub-resolution IC scaling |
| title_full | Design technology co-optimization in the era of sub-resolution IC scaling Lars Liebmann, Kaushik Vaidyanathan, and Lawrence Pileggi |
| title_fullStr | Design technology co-optimization in the era of sub-resolution IC scaling Lars Liebmann, Kaushik Vaidyanathan, and Lawrence Pileggi |
| title_full_unstemmed | Design technology co-optimization in the era of sub-resolution IC scaling Lars Liebmann, Kaushik Vaidyanathan, and Lawrence Pileggi |
| title_short | Design technology co-optimization in the era of sub-resolution IC scaling |
| title_sort | design technology co optimization in the era of sub resolution ic scaling |
| topic | Integrated circuits / Design and construction Lithography, Electron beam |
| topic_facet | Integrated circuits / Design and construction Lithography, Electron beam |
| url | https://doi.org/10.1117/3.2217861 |
| volume_link | (DE-604)BV044913200 |
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