Verification techniques for system-level design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Morgan Kaufmann Publishers
c2008
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references and index |
| Beschreibung: | viii, 240 p. |
| ISBN: | 9780123706164 0123706165 |
Internformat
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| 100 | 1 | |a Fujita, Masahiro |d 1956- |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Verification techniques for system-level design |c Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| 264 | 1 | |a Amsterdam |b Morgan Kaufmann Publishers |c c2008 | |
| 300 | |a viii, 240 p. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 490 | 0 | |a Morgan Kaufmann series in systems on silicon | |
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Systems on a chip |x Testing | |
| 650 | 4 | |a Integrated circuits |x Verification | |
| 650 | 4 | |a Formal methods (Computer science) | |
| 650 | 0 | 7 | |a Hardwareverifikation |0 (DE-588)4214982-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a LSI |0 (DE-588)4168200-2 |2 gnd |9 rswk-swf |
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| 700 | 1 | |a Ghosh, Indradeep |d 1970- |e Sonstige |4 oth | |
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Datensatz im Suchindex
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| any_adam_object | |
| author | Fujita, Masahiro 1956- |
| author_facet | Fujita, Masahiro 1956- |
| author_role | aut |
| author_sort | Fujita, Masahiro 1956- |
| author_variant | m f mf |
| building | Verbundindex |
| bvnumber | BV044127494 |
| classification_rvk | ZN 4904 |
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| ctrlnum | (ZDB-30-PAD)EBC318151 (ZDB-89-EBL)EBL318151 (OCoLC)437191662 (DE-599)BVBBV044127494 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV044127494 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:44:30Z |
| institution | BVB |
| isbn | 9780123706164 0123706165 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029534339 |
| oclc_num | 437191662 |
| open_access_boolean | |
| physical | viii, 240 p. |
| psigel | ZDB-30-PAD |
| publishDate | 2008 |
| publishDateSearch | 2008 |
| publishDateSort | 2008 |
| publisher | Morgan Kaufmann Publishers |
| record_format | marc |
| series2 | Morgan Kaufmann series in systems on silicon |
| spelling | Fujita, Masahiro 1956- Verfasser aut Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad Amsterdam Morgan Kaufmann Publishers c2008 viii, 240 p. txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes bibliographical references and index Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf LSI (DE-588)4168200-2 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf System-on-Chip (DE-588)4740357-3 s LSI (DE-588)4168200-2 s Hardwareverifikation (DE-588)4214982-4 s 1\p DE-604 Ghosh, Indradeep 1970- Sonstige oth Prasad, Mukul Sonstige oth Erscheint auch als Druck-Ausgabe, Paperback 978-0-12-370616-4 Erscheint auch als Druck-Ausgabe, Paperback 0-12-370616-5 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Fujita, Masahiro 1956- Verification techniques for system-level design Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd LSI (DE-588)4168200-2 gnd System-on-Chip (DE-588)4740357-3 gnd |
| subject_GND | (DE-588)4214982-4 (DE-588)4168200-2 (DE-588)4740357-3 |
| title | Verification techniques for system-level design |
| title_auth | Verification techniques for system-level design |
| title_exact_search | Verification techniques for system-level design |
| title_full | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_fullStr | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_full_unstemmed | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_short | Verification techniques for system-level design |
| title_sort | verification techniques for system level design |
| topic | Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd LSI (DE-588)4168200-2 gnd System-on-Chip (DE-588)4740357-3 gnd |
| topic_facet | Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) Hardwareverifikation LSI System-on-Chip |
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