Design recipes for FPGAs:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Newnes
2007
|
| Schlagworte: | |
| Beschreibung: | Includes bibliographical references (p. [284]-285) and index |
| Beschreibung: | xxii, 289 p. |
| ISBN: | 9780750668453 0750668458 |
Internformat
MARC
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| 100 | 1 | |a Wilson, Peter R. |d 1939- |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Design recipes for FPGAs |c Peter R. Wilson |
| 264 | 1 | |a Amsterdam |b Newnes |c 2007 | |
| 300 | |a xxii, 289 p. | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Includes bibliographical references (p. [284]-285) and index | ||
| 650 | 4 | |a Field programmable gate arrays |x Design and construction | |
| 650 | 4 | |a Gate array circuits | |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
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Datensatz im Suchindex
| _version_ | 1804177209437454336 |
|---|---|
| any_adam_object | |
| author | Wilson, Peter R. 1939- |
| author_facet | Wilson, Peter R. 1939- |
| author_role | aut |
| author_sort | Wilson, Peter R. 1939- |
| author_variant | p r w pr prw |
| building | Verbundindex |
| bvnumber | BV044125210 |
| collection | ZDB-30-PAD |
| ctrlnum | (ZDB-30-PAD)EBC305549 (ZDB-89-EBL)EBL305549 (OCoLC)476083031 (DE-599)BVBBV044125210 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV044125210 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:44:26Z |
| institution | BVB |
| isbn | 9780750668453 0750668458 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029532055 |
| oclc_num | 476083031 |
| open_access_boolean | |
| physical | xxii, 289 p. |
| psigel | ZDB-30-PAD |
| publishDate | 2007 |
| publishDateSearch | 2007 |
| publishDateSort | 2007 |
| publisher | Newnes |
| record_format | marc |
| spelling | Wilson, Peter R. 1939- Verfasser aut Design recipes for FPGAs Peter R. Wilson Amsterdam Newnes 2007 xxii, 289 p. txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references (p. [284]-285) and index Field programmable gate arrays Design and construction Gate array circuits Field programmable gate array (DE-588)4347749-5 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s VERILOG (DE-588)4268385-3 s VHDL (DE-588)4254792-1 s 1\p DE-604 Erscheint auch als Druck-Ausgabe, Paperback 978-0-7506-6845-3 Erscheint auch als Druck-Ausgabe, Paperback 0-7506-6845-8 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Wilson, Peter R. 1939- Design recipes for FPGAs Field programmable gate arrays Design and construction Gate array circuits Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| subject_GND | (DE-588)4347749-5 (DE-588)4268385-3 (DE-588)4254792-1 |
| title | Design recipes for FPGAs |
| title_auth | Design recipes for FPGAs |
| title_exact_search | Design recipes for FPGAs |
| title_full | Design recipes for FPGAs Peter R. Wilson |
| title_fullStr | Design recipes for FPGAs Peter R. Wilson |
| title_full_unstemmed | Design recipes for FPGAs Peter R. Wilson |
| title_short | Design recipes for FPGAs |
| title_sort | design recipes for fpgas |
| topic | Field programmable gate arrays Design and construction Gate array circuits Field programmable gate array (DE-588)4347749-5 gnd VERILOG (DE-588)4268385-3 gnd VHDL (DE-588)4254792-1 gnd |
| topic_facet | Field programmable gate arrays Design and construction Gate array circuits Field programmable gate array VERILOG VHDL |
| work_keys_str_mv | AT wilsonpeterr designrecipesforfpgas |