VLSI test principles and architectures: design for testability
Gespeichert in:
Format: | Elektronisch E-Book |
---|---|
Sprache: | English |
Veröffentlicht: |
Amsterdam
Elsevier Morgan Kaufmann Publishers
c2006
|
Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
Schlagworte: | |
Beschreibung: | Includes bibliographical references and index |
Beschreibung: | xxx, 777 p. 25 cm |
ISBN: | 9780123705976 |
Internformat
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Datensatz im Suchindex
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dewey-ones | 621 - Applied physics |
dewey-raw | 621.39/5 |
dewey-search | 621.39/5 |
dewey-sort | 3621.39 15 |
dewey-tens | 620 - Engineering and allied operations |
discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
format | Electronic eBook |
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id | DE-604.BV044123115 |
illustrated | Not Illustrated |
indexdate | 2024-07-10T07:44:23Z |
institution | BVB |
isbn | 9780123705976 |
language | English |
oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029529960 |
oclc_num | 162573568 |
open_access_boolean | |
physical | xxx, 777 p. 25 cm |
psigel | ZDB-30-PAD |
publishDate | 2006 |
publishDateSearch | 2006 |
publishDateSort | 2006 |
publisher | Elsevier Morgan Kaufmann Publishers |
record_format | marc |
series2 | Morgan Kaufmann series in systems on silicon |
spelling | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen Amsterdam Elsevier Morgan Kaufmann Publishers c2006 xxx, 777 p. 25 cm txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes bibliographical references and index Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd rswk-swf Testen (DE-588)4367264-4 gnd rswk-swf VLSI (DE-588)4117388-0 s Testen (DE-588)4367264-4 s 1\p DE-604 Wang, Laung-Terng Sonstige oth Wu, Cheng-Wen Sonstige oth Wen, Xiaoqing Sonstige oth Erscheint auch als Druck-Ausgabe, Hardcover 0-12-370597-5 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
spellingShingle | VLSI test principles and architectures design for testability Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd Testen (DE-588)4367264-4 gnd |
subject_GND | (DE-588)4117388-0 (DE-588)4367264-4 |
title | VLSI test principles and architectures design for testability |
title_auth | VLSI test principles and architectures design for testability |
title_exact_search | VLSI test principles and architectures design for testability |
title_full | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
title_fullStr | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
title_full_unstemmed | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
title_short | VLSI test principles and architectures |
title_sort | vlsi test principles and architectures design for testability |
title_sub | design for testability |
topic | Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI (DE-588)4117388-0 gnd Testen (DE-588)4367264-4 gnd |
topic_facet | Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI Testen |
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