Practical design verification:
Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model check...
Gespeichert in:
| Weitere Verfasser: | , |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Cambridge
Cambridge University Press
2009
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| Schlagworte: | |
| Online-Zugang: | BSB01 FHN01 URL des Erstveröffentlichers |
| Zusammenfassung: | Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT) |
| Beschreibung: | Title from publisher's bibliographic system (viewed on 05 Oct 2015) |
| Beschreibung: | 1 online resource (xi, 276 pages) |
| ISBN: | 9780511626913 |
| DOI: | 10.1017/CBO9780511626913 |
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| 505 | 8 | |a Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva | |
| 520 | |a Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT) | ||
| 650 | 4 | |a Integrated circuits / Verification | |
| 700 | 1 | |a Pradhan, Dhiraj K. |4 edt | |
| 700 | 1 | |a Harris, Ian G. |4 edt | |
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| contents | Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva |
| ctrlnum | (ZDB-20-CBO)CR9780511626913 (OCoLC)851167826 (DE-599)BVBBV043944351 |
| dewey-full | 621.3815/48 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/48 |
| dewey-search | 621.3815/48 |
| dewey-sort | 3621.3815 248 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1017/CBO9780511626913 |
| format | Electronic eBook |
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| id | DE-604.BV043944351 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:39:21Z |
| institution | BVB |
| isbn | 9780511626913 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029353321 |
| oclc_num | 851167826 |
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| physical | 1 online resource (xi, 276 pages) |
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| publisher | Cambridge University Press |
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| spelling | Practical design verification edited by Dhiraj K. Pradhan, Ian G. Harris Cambridge Cambridge University Press 2009 1 online resource (xi, 276 pages) txt rdacontent c rdamedia cr rdacarrier Title from publisher's bibliographic system (viewed on 05 Oct 2015) Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT) Integrated circuits / Verification Pradhan, Dhiraj K. edt Harris, Ian G. edt Erscheint auch als Druckausgabe 978-0-521-85972-1 https://doi.org/10.1017/CBO9780511626913 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Practical design verification Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva Integrated circuits / Verification |
| title | Practical design verification |
| title_auth | Practical design verification |
| title_exact_search | Practical design verification |
| title_full | Practical design verification edited by Dhiraj K. Pradhan, Ian G. Harris |
| title_fullStr | Practical design verification edited by Dhiraj K. Pradhan, Ian G. Harris |
| title_full_unstemmed | Practical design verification edited by Dhiraj K. Pradhan, Ian G. Harris |
| title_short | Practical design verification |
| title_sort | practical design verification |
| topic | Integrated circuits / Verification |
| topic_facet | Integrated circuits / Verification |
| url | https://doi.org/10.1017/CBO9780511626913 |
| work_keys_str_mv | AT pradhandhirajk practicaldesignverification AT harrisiang practicaldesignverification |