A designer's guide to asynchronous VLSI:
Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standa...
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| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Cambridge
Cambridge University Press
2010
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| Subjects: | |
| Online Access: | BSB01 FHN01 Volltext |
| Summary: | Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems |
| Item Description: | Title from publisher's bibliographic system (viewed on 05 Oct 2015) |
| Physical Description: | 1 online resource (xii, 339 pages) |
| ISBN: | 9780511674730 |
| DOI: | 10.1017/CBO9780511674730 |
Staff View
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| contents | Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith |
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| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1017/CBO9780511674730 |
| format | Electronic eBook |
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| id | DE-604.BV043943018 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:39:18Z |
| institution | BVB |
| isbn | 9780511674730 |
| language | English |
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| physical | 1 online resource (xii, 339 pages) |
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| publishDate | 2010 |
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| publisher | Cambridge University Press |
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| spelling | Beerel, Peter A. Verfasser aut A designer's guide to asynchronous VLSI Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti Cambridge Cambridge University Press 2010 1 online resource (xii, 339 pages) txt rdacontent c rdamedia cr rdacarrier Title from publisher's bibliographic system (viewed on 05 Oct 2015) Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems Integrated circuits / Very large scale integration / Computer-aided design Integrated circuits / Very large scale integration / Design and construction Ozdag, Recep O. Sonstige oth Ferretti, Marcos Sonstige oth Erscheint auch als Druckausgabe 978-0-521-87244-7 https://doi.org/10.1017/CBO9780511674730 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Beerel, Peter A. A designer's guide to asynchronous VLSI Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith Integrated circuits / Very large scale integration / Computer-aided design Integrated circuits / Very large scale integration / Design and construction |
| title | A designer's guide to asynchronous VLSI |
| title_auth | A designer's guide to asynchronous VLSI |
| title_exact_search | A designer's guide to asynchronous VLSI |
| title_full | A designer's guide to asynchronous VLSI Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti |
| title_fullStr | A designer's guide to asynchronous VLSI Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti |
| title_full_unstemmed | A designer's guide to asynchronous VLSI Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti |
| title_short | A designer's guide to asynchronous VLSI |
| title_sort | a designer s guide to asynchronous vlsi |
| topic | Integrated circuits / Very large scale integration / Computer-aided design Integrated circuits / Very large scale integration / Design and construction |
| topic_facet | Integrated circuits / Very large scale integration / Computer-aided design Integrated circuits / Very large scale integration / Design and construction |
| url | https://doi.org/10.1017/CBO9780511674730 |
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