A designer's guide to asynchronous VLSI:
Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standa...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Cambridge
Cambridge University Press
2010
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| Schlagworte: | |
| Online-Zugang: | BSB01 FHN01 URL des Erstveröffentlichers |
| Zusammenfassung: | Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems |
| Beschreibung: | Title from publisher's bibliographic system (viewed on 05 Oct 2015) |
| Beschreibung: | 1 online resource (xii, 339 pages) |
| ISBN: | 9780511674730 |
| DOI: | 10.1017/CBO9780511674730 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV043943018 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 161206s2010 |||| o||u| ||||||eng d | ||
| 020 | |a 9780511674730 |c Online |9 978-0-511-67473-0 | ||
| 024 | 7 | |a 10.1017/CBO9780511674730 |2 doi | |
| 035 | |a (ZDB-20-CBO)CR9780511674730 | ||
| 035 | |a (OCoLC)839031879 | ||
| 035 | |a (DE-599)BVBBV043943018 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-12 |a DE-92 | ||
| 082 | 0 | |a 621.39/5 |2 22 | |
| 084 | |a ZN 4952 |0 (DE-625)157425: |2 rvk | ||
| 100 | 1 | |a Beerel, Peter A. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a A designer's guide to asynchronous VLSI |c Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti |
| 264 | 1 | |a Cambridge |b Cambridge University Press |c 2010 | |
| 300 | |a 1 online resource (xii, 339 pages) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Title from publisher's bibliographic system (viewed on 05 Oct 2015) | ||
| 505 | 8 | |a Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith | |
| 520 | |a Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems | ||
| 650 | 4 | |a Integrated circuits / Very large scale integration / Computer-aided design | |
| 650 | 4 | |a Integrated circuits / Very large scale integration / Design and construction | |
| 700 | 1 | |a Ozdag, Recep O. |e Sonstige |4 oth | |
| 700 | 1 | |a Ferretti, Marcos |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druckausgabe |z 978-0-521-87244-7 |
| 856 | 4 | 0 | |u https://doi.org/10.1017/CBO9780511674730 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-20-CBO | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-029351989 | ||
| 966 | e | |u https://doi.org/10.1017/CBO9780511674730 |l BSB01 |p ZDB-20-CBO |q BSB_PDA_CBO |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1017/CBO9780511674730 |l FHN01 |p ZDB-20-CBO |q FHN_PDA_CBO |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804176886549446656 |
|---|---|
| any_adam_object | |
| author | Beerel, Peter A. |
| author_facet | Beerel, Peter A. |
| author_role | aut |
| author_sort | Beerel, Peter A. |
| author_variant | p a b pa pab |
| building | Verbundindex |
| bvnumber | BV043943018 |
| classification_rvk | ZN 4952 |
| collection | ZDB-20-CBO |
| contents | Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith |
| ctrlnum | (ZDB-20-CBO)CR9780511674730 (OCoLC)839031879 (DE-599)BVBBV043943018 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1017/CBO9780511674730 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02914nmm a2200445zc 4500</leader><controlfield tag="001">BV043943018</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">161206s2010 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780511674730</subfield><subfield code="c">Online</subfield><subfield code="9">978-0-511-67473-0</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1017/CBO9780511674730</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-20-CBO)CR9780511674730</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)839031879</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV043943018</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-12</subfield><subfield code="a">DE-92</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">22</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4952</subfield><subfield code="0">(DE-625)157425:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Beerel, Peter A.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">A designer's guide to asynchronous VLSI</subfield><subfield code="c">Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cambridge</subfield><subfield code="b">Cambridge University Press</subfield><subfield code="c">2010</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (xii, 339 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Title from publisher's bibliographic system (viewed on 05 Oct 2015)</subfield></datafield><datafield tag="505" ind1="8" ind2=" "><subfield code="a">Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits / Very large scale integration / Computer-aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits / Very large scale integration / Design and construction</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ozdag, Recep O.</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Ferretti, Marcos</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druckausgabe</subfield><subfield code="z">978-0-521-87244-7</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1017/CBO9780511674730</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-20-CBO</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-029351989</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1017/CBO9780511674730</subfield><subfield code="l">BSB01</subfield><subfield code="p">ZDB-20-CBO</subfield><subfield code="q">BSB_PDA_CBO</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1017/CBO9780511674730</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-20-CBO</subfield><subfield code="q">FHN_PDA_CBO</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV043943018 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:39:18Z |
| institution | BVB |
| isbn | 9780511674730 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029351989 |
| oclc_num | 839031879 |
| open_access_boolean | |
| owner | DE-12 DE-92 |
| owner_facet | DE-12 DE-92 |
| physical | 1 online resource (xii, 339 pages) |
| psigel | ZDB-20-CBO ZDB-20-CBO BSB_PDA_CBO ZDB-20-CBO FHN_PDA_CBO |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Cambridge University Press |
| record_format | marc |
| spelling | Beerel, Peter A. Verfasser aut A designer's guide to asynchronous VLSI Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti Cambridge Cambridge University Press 2010 1 online resource (xii, 339 pages) txt rdacontent c rdamedia cr rdacarrier Title from publisher's bibliographic system (viewed on 05 Oct 2015) Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems Integrated circuits / Very large scale integration / Computer-aided design Integrated circuits / Very large scale integration / Design and construction Ozdag, Recep O. Sonstige oth Ferretti, Marcos Sonstige oth Erscheint auch als Druckausgabe 978-0-521-87244-7 https://doi.org/10.1017/CBO9780511674730 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Beerel, Peter A. A designer's guide to asynchronous VLSI Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith Integrated circuits / Very large scale integration / Computer-aided design Integrated circuits / Very large scale integration / Design and construction |
| title | A designer's guide to asynchronous VLSI |
| title_auth | A designer's guide to asynchronous VLSI |
| title_exact_search | A designer's guide to asynchronous VLSI |
| title_full | A designer's guide to asynchronous VLSI Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti |
| title_fullStr | A designer's guide to asynchronous VLSI Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti |
| title_full_unstemmed | A designer's guide to asynchronous VLSI Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti |
| title_short | A designer's guide to asynchronous VLSI |
| title_sort | a designer s guide to asynchronous vlsi |
| topic | Integrated circuits / Very large scale integration / Computer-aided design Integrated circuits / Very large scale integration / Design and construction |
| topic_facet | Integrated circuits / Very large scale integration / Computer-aided design Integrated circuits / Very large scale integration / Design and construction |
| url | https://doi.org/10.1017/CBO9780511674730 |
| work_keys_str_mv | AT beerelpetera adesignersguidetoasynchronousvlsi AT ozdagrecepo adesignersguidetoasynchronousvlsi AT ferrettimarcos adesignersguidetoasynchronousvlsi |