This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations,...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	Baer, Jean-Loup (VerfasserIn)
Format:	Elektronisch E-Book
Sprache:	English
Veröffentlicht:	Cambridge Cambridge University Press 2010
Schlagworte:	Microprocessors Computer architecture
Online-Zugang:	BSB01 FHN01 Volltext
Zusammenfassung:	This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers • Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations • Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors • State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity
Beschreibung:	Title from publisher's bibliographic system (viewed on 05 Oct 2015)
Beschreibung:	1 online resource (xiv, 367 pages)
ISBN:	9780511811258
DOI:	10.1017/CBO9780511811258