APA (7th ed.) Citation

Lourenço, N., Martins, R., & Horta, N. C. G. (2017). Automatic analog IC sizing and optimization constrained with PVT corners and layout effects. Springer. https://doi.org/10.1007/978-3-319-42037-0

Chicago Style (17th ed.) Citation

Lourenço, Nuno, Ricardo Martins, and Nuno C. G. Horta. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. Cham: Springer, 2017. https://doi.org/10.1007/978-3-319-42037-0.

MLA (9th ed.) Citation

Lourenço, Nuno, et al. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. Springer, 2017. https://doi.org/10.1007/978-3-319-42037-0.