Formal verification: an essential toolkit for modern VLSI design
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| Main Authors: | , , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Amsterdam
Elsevier, Morgan Kaufmann
[2015]
|
| Subjects: | |
| Physical Description: | xvii, 353 Seiten Illustrationen, Diagramme |
| ISBN: | 9780128007273 |
Staff View
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Record in the Search Index
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| id | DE-604.BV043807013 |
| illustrated | Illustrated |
| indexdate | 2025-03-05T05:00:27Z |
| institution | BVB |
| isbn | 9780128007273 |
| language | English |
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| physical | xvii, 353 Seiten Illustrationen, Diagramme |
| publishDate | 2015 |
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| publisher | Elsevier, Morgan Kaufmann |
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| spelling | Seligman, Erik Verfasser (DE-588)1102203785 aut Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar Amsterdam Elsevier, Morgan Kaufmann [2015] © 2015 xvii, 353 Seiten Illustrationen, Diagramme txt rdacontent n rdamedia nc rdacarrier Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Schubert, Tom Verfasser aut Kumar, M. V. Achutha Kiran Verfasser aut Erscheint auch als Online-Ausgabe 0-12-800815-6 Erscheint auch als Online-Ausgabe 978-0-12-800815-7 |
| spellingShingle | Seligman, Erik Schubert, Tom Kumar, M. V. Achutha Kiran Formal verification an essential toolkit for modern VLSI design Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) |
| title | Formal verification an essential toolkit for modern VLSI design |
| title_auth | Formal verification an essential toolkit for modern VLSI design |
| title_exact_search | Formal verification an essential toolkit for modern VLSI design |
| title_full | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_fullStr | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_full_unstemmed | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_short | Formal verification |
| title_sort | formal verification an essential toolkit for modern vlsi design |
| title_sub | an essential toolkit for modern VLSI design |
| topic | Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) |
| topic_facet | Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) |
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