Formal verification: an essential toolkit for modern VLSI design
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Elsevier, Morgan Kaufmann
[2015]
|
| Schlagworte: | |
| Beschreibung: | xvii, 353 Seiten Illustrationen, Diagramme |
| ISBN: | 9780128007273 |
Internformat
MARC
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| 007 | t | ||
| 008 | 160929s2015 a||| |||| 00||| eng d | ||
| 020 | |a 9780128007273 |c print |9 978-0-12-800727-3 | ||
| 035 | |a (OCoLC)1344235110 | ||
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| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
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| 100 | 1 | |a Seligman, Erik |e Verfasser |0 (DE-588)1102203785 |4 aut | |
| 245 | 1 | 0 | |a Formal verification |b an essential toolkit for modern VLSI design |c Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| 264 | 1 | |a Amsterdam |b Elsevier, Morgan Kaufmann |c [2015] | |
| 264 | 4 | |c © 2015 | |
| 300 | |a xvii, 353 Seiten |b Illustrationen, Diagramme | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 4 | |a Electronic circuits |x Testing | |
| 650 | 4 | |a Integrated circuits |x Very large scale integration |x Design and construction | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 700 | 1 | |a Schubert, Tom |e Verfasser |4 aut | |
| 700 | 1 | |a Kumar, M. V. Achutha Kiran |e Verfasser |4 aut | |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |z 0-12-800815-6 |
| 776 | 0 | 8 | |i Erscheint auch als |n Online-Ausgabe |z 978-0-12-800815-7 |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-029218331 | ||
Datensatz im Suchindex
| _version_ | 1804176653149011968 |
|---|---|
| any_adam_object | |
| author | Seligman, Erik Schubert, Tom Kumar, M. V. Achutha Kiran |
| author_GND | (DE-588)1102203785 |
| author_facet | Seligman, Erik Schubert, Tom Kumar, M. V. Achutha Kiran |
| author_role | aut aut aut |
| author_sort | Seligman, Erik |
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| building | Verbundindex |
| bvnumber | BV043807013 |
| ctrlnum | (OCoLC)1344235110 (DE-599)BVBBV043807013 |
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| id | DE-604.BV043807013 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T07:35:36Z |
| institution | BVB |
| isbn | 9780128007273 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029218331 |
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| physical | xvii, 353 Seiten Illustrationen, Diagramme |
| publishDate | 2015 |
| publishDateSearch | 2015 |
| publishDateSort | 2015 |
| publisher | Elsevier, Morgan Kaufmann |
| record_format | marc |
| spelling | Seligman, Erik Verfasser (DE-588)1102203785 aut Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar Amsterdam Elsevier, Morgan Kaufmann [2015] © 2015 xvii, 353 Seiten Illustrationen, Diagramme txt rdacontent n rdamedia nc rdacarrier Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) Schubert, Tom Verfasser aut Kumar, M. V. Achutha Kiran Verfasser aut Erscheint auch als Online-Ausgabe 0-12-800815-6 Erscheint auch als Online-Ausgabe 978-0-12-800815-7 |
| spellingShingle | Seligman, Erik Schubert, Tom Kumar, M. V. Achutha Kiran Formal verification an essential toolkit for modern VLSI design Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) |
| title | Formal verification an essential toolkit for modern VLSI design |
| title_auth | Formal verification an essential toolkit for modern VLSI design |
| title_exact_search | Formal verification an essential toolkit for modern VLSI design |
| title_full | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_fullStr | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_full_unstemmed | Formal verification an essential toolkit for modern VLSI design Erik Seligman, Tom Schubert, M.V. Achutha Kiran Kumar |
| title_short | Formal verification |
| title_sort | formal verification an essential toolkit for modern vlsi design |
| title_sub | an essential toolkit for modern VLSI design |
| topic | Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) |
| topic_facet | Electronic circuits Testing Integrated circuits Very large scale integration Design and construction Verilog (Computer hardware description language) |
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