Formal Verification: An Essential Toolkit for Modern VLSI Design
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically expl...
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| Main Author: | |
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| Format: | Electronic eBook |
| Language: | English |
| Published: |
Elsevier Science
2015
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| Subjects: | |
| Online Access: | FAW01 |
| Summary: | Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulationUnderstand formal verification tools and how they differ from simulation toolsCreate instant test benches to gain insight into how models work and find initial bugsLearn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems |
| Item Description: | Description based on publisher supplied metadata and other sources |
| Physical Description: | 1 online resource (372 pages) |
| ISBN: | 9780128008157 9780128007273 |
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| spelling | Seligman, Erik Verfasser aut Formal Verification An Essential Toolkit for Modern VLSI Design Elsevier Science 2015 © 2015 1 online resource (372 pages) txt rdacontent c rdamedia cr rdacarrier Description based on publisher supplied metadata and other sources Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulationUnderstand formal verification tools and how they differ from simulation toolsCreate instant test benches to gain insight into how models work and find initial bugsLearn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems Electronic circuits -- Testing Integrated circuits -- Very large scale integration -- Design and construction Verilog (Computer hardware description language) Schubert, Tom Sonstige oth Kumar, M V Achutha Kiran Sonstige oth Erscheint auch als Druck-Ausgabe Seligman, Erik Formal Verification : An Essential Toolkit for Modern VLSI Design |
| spellingShingle | Seligman, Erik Formal Verification An Essential Toolkit for Modern VLSI Design Electronic circuits -- Testing Integrated circuits -- Very large scale integration -- Design and construction Verilog (Computer hardware description language) |
| title | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_auth | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_exact_search | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_full | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_fullStr | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_full_unstemmed | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_short | Formal Verification |
| title_sort | formal verification an essential toolkit for modern vlsi design |
| title_sub | An Essential Toolkit for Modern VLSI Design |
| topic | Electronic circuits -- Testing Integrated circuits -- Very large scale integration -- Design and construction Verilog (Computer hardware description language) |
| topic_facet | Electronic circuits -- Testing Integrated circuits -- Very large scale integration -- Design and construction Verilog (Computer hardware description language) |
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