Formal Verification: An Essential Toolkit for Modern VLSI Design
Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically expl...
Gespeichert in:
| 1. Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Elsevier Science
2015
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| Schlagworte: | |
| Online-Zugang: | FAW01 |
| Zusammenfassung: | Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulationUnderstand formal verification tools and how they differ from simulation toolsCreate instant test benches to gain insight into how models work and find initial bugsLearn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems |
| Beschreibung: | Description based on publisher supplied metadata and other sources |
| Beschreibung: | 1 online resource (372 pages) |
| ISBN: | 9780128008157 9780128007273 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV043622379 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 160616s2015 |||| o||u| ||||||eng d | ||
| 020 | |a 9780128008157 |9 978-0-12-800815-7 | ||
| 020 | |a 9780128007273 |c Print |9 978-0-12-800727-3 | ||
| 035 | |a (ZDB-30-PQE)EBC2111103 | ||
| 035 | |a (ZDB-89-EBL)EBL2111103 | ||
| 035 | |a (ZDB-38-EBR)ebr11082359 | ||
| 035 | |a (OCoLC)915311665 | ||
| 035 | |a (DE-599)BVBBV043622379 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-1046 | ||
| 082 | 0 | |a 621.3815/48 | |
| 100 | 1 | |a Seligman, Erik |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Formal Verification |b An Essential Toolkit for Modern VLSI Design |
| 264 | 1 | |b Elsevier Science |c 2015 | |
| 264 | 4 | |c © 2015 | |
| 300 | |a 1 online resource (372 pages) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Description based on publisher supplied metadata and other sources | ||
| 520 | |a Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulationUnderstand formal verification tools and how they differ from simulation toolsCreate instant test benches to gain insight into how models work and find initial bugsLearn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems | ||
| 650 | 4 | |a Electronic circuits -- Testing | |
| 650 | 4 | |a Integrated circuits -- Very large scale integration -- Design and construction | |
| 650 | 4 | |a Verilog (Computer hardware description language) | |
| 700 | 1 | |a Schubert, Tom |e Sonstige |4 oth | |
| 700 | 1 | |a Kumar, M V Achutha Kiran |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe |a Seligman, Erik |t Formal Verification : An Essential Toolkit for Modern VLSI Design |
| 912 | |a ZDB-30-PQE |a ZDB-33-ESD |a ZDB-33-EBS | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-029036438 | ||
| 966 | e | |u http://www.sciencedirect.com/science/book/9780128007273 |l FAW01 |p ZDB-33-ESD |q FAW_PDA_ESD |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804176360302706688 |
|---|---|
| any_adam_object | |
| author | Seligman, Erik |
| author_facet | Seligman, Erik |
| author_role | aut |
| author_sort | Seligman, Erik |
| author_variant | e s es |
| building | Verbundindex |
| bvnumber | BV043622379 |
| collection | ZDB-30-PQE ZDB-33-ESD ZDB-33-EBS |
| ctrlnum | (ZDB-30-PQE)EBC2111103 (ZDB-89-EBL)EBL2111103 (ZDB-38-EBR)ebr11082359 (OCoLC)915311665 (DE-599)BVBBV043622379 |
| dewey-full | 621.3815/48 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815/48 |
| dewey-search | 621.3815/48 |
| dewey-sort | 3621.3815 248 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02915nmm a2200445zc 4500</leader><controlfield tag="001">BV043622379</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">160616s2015 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780128008157</subfield><subfield code="9">978-0-12-800815-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780128007273</subfield><subfield code="c">Print</subfield><subfield code="9">978-0-12-800727-3</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-30-PQE)EBC2111103</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-89-EBL)EBL2111103</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-38-EBR)ebr11082359</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)915311665</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV043622379</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-1046</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815/48</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Seligman, Erik</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Formal Verification</subfield><subfield code="b">An Essential Toolkit for Modern VLSI Design</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="b">Elsevier Science</subfield><subfield code="c">2015</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">© 2015</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 online resource (372 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Description based on publisher supplied metadata and other sources</subfield></datafield><datafield tag="520" ind1=" " ind2=" "><subfield code="a">Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulationUnderstand formal verification tools and how they differ from simulation toolsCreate instant test benches to gain insight into how models work and find initial bugsLearn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits -- Testing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits -- Very large scale integration -- Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Verilog (Computer hardware description language)</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Schubert, Tom</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Kumar, M V Achutha Kiran</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe</subfield><subfield code="a">Seligman, Erik</subfield><subfield code="t">Formal Verification : An Essential Toolkit for Modern VLSI Design</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-30-PQE</subfield><subfield code="a">ZDB-33-ESD</subfield><subfield code="a">ZDB-33-EBS</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-029036438</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://www.sciencedirect.com/science/book/9780128007273</subfield><subfield code="l">FAW01</subfield><subfield code="p">ZDB-33-ESD</subfield><subfield code="q">FAW_PDA_ESD</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV043622379 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:30:57Z |
| institution | BVB |
| isbn | 9780128008157 9780128007273 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-029036438 |
| oclc_num | 915311665 |
| open_access_boolean | |
| owner | DE-1046 |
| owner_facet | DE-1046 |
| physical | 1 online resource (372 pages) |
| psigel | ZDB-30-PQE ZDB-33-ESD ZDB-33-EBS ZDB-33-ESD FAW_PDA_ESD |
| publishDate | 2015 |
| publishDateSearch | 2015 |
| publishDateSort | 2015 |
| publisher | Elsevier Science |
| record_format | marc |
| spelling | Seligman, Erik Verfasser aut Formal Verification An Essential Toolkit for Modern VLSI Design Elsevier Science 2015 © 2015 1 online resource (372 pages) txt rdacontent c rdamedia cr rdacarrier Description based on publisher supplied metadata and other sources Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice to help working engineers integrate these techniques into their work. Formal Verification (FV) enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. This can reduce time spent validating designs and more quickly reach a final design for manufacturing. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. After reading this book, readers will be prepared to introduce FV in their organization and effectively deploy FV techniques to increase design and validation productivity. Learn formal verification algorithms to gain full coverage without exhaustive simulationUnderstand formal verification tools and how they differ from simulation toolsCreate instant test benches to gain insight into how models work and find initial bugsLearn from Intel insiders sharing their hard-won knowledge and solutions to complex design problems Electronic circuits -- Testing Integrated circuits -- Very large scale integration -- Design and construction Verilog (Computer hardware description language) Schubert, Tom Sonstige oth Kumar, M V Achutha Kiran Sonstige oth Erscheint auch als Druck-Ausgabe Seligman, Erik Formal Verification : An Essential Toolkit for Modern VLSI Design |
| spellingShingle | Seligman, Erik Formal Verification An Essential Toolkit for Modern VLSI Design Electronic circuits -- Testing Integrated circuits -- Very large scale integration -- Design and construction Verilog (Computer hardware description language) |
| title | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_auth | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_exact_search | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_full | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_fullStr | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_full_unstemmed | Formal Verification An Essential Toolkit for Modern VLSI Design |
| title_short | Formal Verification |
| title_sort | formal verification an essential toolkit for modern vlsi design |
| title_sub | An Essential Toolkit for Modern VLSI Design |
| topic | Electronic circuits -- Testing Integrated circuits -- Very large scale integration -- Design and construction Verilog (Computer hardware description language) |
| topic_facet | Electronic circuits -- Testing Integrated circuits -- Very large scale integration -- Design and construction Verilog (Computer hardware description language) |
| work_keys_str_mv | AT seligmanerik formalverificationanessentialtoolkitformodernvlsidesign AT schuberttom formalverificationanessentialtoolkitformodernvlsidesign AT kumarmvachuthakiran formalverificationanessentialtoolkitformodernvlsidesign |