Cache and Memory Hierarchy Design: A Performance Directed Approach
An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Saint Louis
Elsevier Science
2014
|
| Schriftenreihe: | The Morgan Kaufmann Series in Computer Architecture and Design
|
| Schlagworte: | |
| Online-Zugang: | FAW01 |
| Zusammenfassung: | An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints |
| Beschreibung: | Description based on publisher supplied metadata and other sources |
| Beschreibung: | 1 online resource (238 pages) |
| ISBN: | 9780080500591 9781493303502 |
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Datensatz im Suchindex
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| author | Przybylski, Steven A. |
| author_facet | Przybylski, Steven A. |
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| building | Verbundindex |
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| dewey-full | 621.39/73 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/73 |
| dewey-search | 621.39/73 |
| dewey-sort | 3621.39 273 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| indexdate | 2024-07-10T07:30:54Z |
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| language | English |
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| series2 | The Morgan Kaufmann Series in Computer Architecture and Design |
| spelling | Przybylski, Steven A. Verfasser aut Cache and Memory Hierarchy Design A Performance Directed Approach Saint Louis Elsevier Science 2014 © 1990 1 online resource (238 pages) txt rdacontent c rdamedia cr rdacarrier The Morgan Kaufmann Series in Computer Architecture and Design Description based on publisher supplied metadata and other sources An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints Cache memory Memory hierarchy (Computer science) Cache-Speicher (DE-588)4362843-6 gnd rswk-swf Speicherhierarchie (DE-588)4256353-7 gnd rswk-swf Pufferspeicher (DE-588)4176324-5 gnd rswk-swf Hierarchie (DE-588)4024842-2 gnd rswk-swf Pufferspeicher (DE-588)4176324-5 s 1\p DE-604 Cache-Speicher (DE-588)4362843-6 s 2\p DE-604 Speicherhierarchie (DE-588)4256353-7 s 3\p DE-604 Hierarchie (DE-588)4024842-2 s 4\p DE-604 Erscheint auch als Druck-Ausgabe Przybylski, Steven A . Cache and Memory Hierarchy Design : A Performance Directed Approach 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 3\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 4\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Przybylski, Steven A. Cache and Memory Hierarchy Design A Performance Directed Approach Cache memory Memory hierarchy (Computer science) Cache-Speicher (DE-588)4362843-6 gnd Speicherhierarchie (DE-588)4256353-7 gnd Pufferspeicher (DE-588)4176324-5 gnd Hierarchie (DE-588)4024842-2 gnd |
| subject_GND | (DE-588)4362843-6 (DE-588)4256353-7 (DE-588)4176324-5 (DE-588)4024842-2 |
| title | Cache and Memory Hierarchy Design A Performance Directed Approach |
| title_auth | Cache and Memory Hierarchy Design A Performance Directed Approach |
| title_exact_search | Cache and Memory Hierarchy Design A Performance Directed Approach |
| title_full | Cache and Memory Hierarchy Design A Performance Directed Approach |
| title_fullStr | Cache and Memory Hierarchy Design A Performance Directed Approach |
| title_full_unstemmed | Cache and Memory Hierarchy Design A Performance Directed Approach |
| title_short | Cache and Memory Hierarchy Design |
| title_sort | cache and memory hierarchy design a performance directed approach |
| title_sub | A Performance Directed Approach |
| topic | Cache memory Memory hierarchy (Computer science) Cache-Speicher (DE-588)4362843-6 gnd Speicherhierarchie (DE-588)4256353-7 gnd Pufferspeicher (DE-588)4176324-5 gnd Hierarchie (DE-588)4024842-2 gnd |
| topic_facet | Cache memory Memory hierarchy (Computer science) Cache-Speicher Speicherhierarchie Pufferspeicher Hierarchie |
| work_keys_str_mv | AT przybylskistevena cacheandmemoryhierarchydesignaperformancedirectedapproach |