Holdings: Digital logic design using verilog

Digital logic design using verilog: coding and RTL synthesis

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Bibliographic Details
Main Author:	Taraate, Vaibbhav (Author)
Format:	Electronic eBook
Language:	English
Published:	[New Delhi] Springer [2016]
Subjects:	Engineering Logic design Electronics Microelectronics Electronic circuits Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Ingenieurwissenschaften
Online Access:	BTU01 FAB01 FAW01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext Inhaltsverzeichnis Abstract
Physical Description:	1 Online-Ressource (XXIII, 416 p. 267 illus., 226 illus. in color)
ISBN:	9788132227915
DOI:	10.1007/978-81-322-2791-5

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MARC


LEADER	00000nmm a2200000zc 4500
001	BV043579778
003	DE-604
005	20160816
007	cr\|uuu---uuuuu
008	160601s2016 \|\|\|\| o\|\|u\| \|\|\|\|\|\|eng d
020			\|a 9788132227915 \|c Online \|9 978-81-322-2791-5
024	7		\|a 10.1007/978-81-322-2791-5 \|2 doi
035			\|a (ZDB-2-ENG)978-81-322-2791-5
035			\|a (OCoLC)951067989
035			\|a (DE-599)BVBBV043579778
040			\|a DE-604 \|b ger \|e rda
041	0		\|a eng
049			\|a DE-706 \|a DE-1046 \|a DE-1043 \|a DE-Aug4 \|a DE-898 \|a DE-861 \|a DE-573 \|a DE-859 \|a DE-863 \|a DE-634 \|a DE-862 \|a DE-92
082	0		\|a 621.3815 \|2 23
100	1		\|a Taraate, Vaibbhav \|e Verfasser \|4 aut
245	1	0	\|a Digital logic design using verilog \|b coding and RTL synthesis \|c Vaibbhav Taraate
264		1	\|a [New Delhi] \|b Springer \|c [2016]
264		4	\|c © 2016
300			\|a 1 Online-Ressource (XXIII, 416 p. 267 illus., 226 illus. in color)
336			\|b txt \|2 rdacontent
337			\|b c \|2 rdamedia
338			\|b cr \|2 rdacarrier
650		4	\|a Engineering
650		4	\|a Logic design
650		4	\|a Electronics
650		4	\|a Microelectronics
650		4	\|a Electronic circuits
650		4	\|a Circuits and Systems
650		4	\|a Electronics and Microelectronics, Instrumentation
650		4	\|a Logic Design
650		4	\|a Ingenieurwissenschaften
776	0	8	\|i Erscheint auch als \|n Druckausgabe \|z 978-81-322-2789-2
856	4	0	\|u https://doi.org/10.1007/978-81-322-2791-5 \|x Verlag \|z URL des Erstveröffentlichers \|3 Volltext
856	4	2	\|m Springer Fremddatenuebernahme \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=028994450&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA \|3 Inhaltsverzeichnis
856	4	2	\|m Springer Fremddatenuebernahme \|q application/pdf \|u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=028994450&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA \|3 Abstract
912			\|a ZDB-2-ENG
940	1		\|q ZDB-2-ENG_2016
999			\|a oai:aleph.bib-bvb.de:BVB01-028994450
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l BTU01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FAB01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FAW01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FHA01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FHI01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FHN01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FHR01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FKE01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FRO01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FWS01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l FWS02 \|p ZDB-2-ENG \|x Verlag \|3 Volltext
966	e		\|u https://doi.org/10.1007/978-81-322-2791-5 \|l UBY01 \|p ZDB-2-ENG \|x Verlag \|3 Volltext

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DE-BY-FWS_katkey	618901
_version_	1824554524951445504
adam_text	DIGITAL LOGIC DESIGN USING VERILOG / TARAATE, VAIBBHAV : 2016 TABLE OF CONTENTS / INHALTSVERZEICHNIS INTRODUCTION COMBINATIONAL LOGIC DESIGN (PART I) COMBINATIONAL LOGIC DESIGN (PART II) COMBINATIONAL DESIGN GUIDELINES SEQUENTIAL LOGIC DESIGN SEQUENTIAL DESIGN GUIDELINES COMPLEX DESIGNS USING VERILOG RTL FINITE STATE MACHINES SIMULATION CONCEPTS AND PLD BASED DESIGNS RTL SYNTHESIS STATIC TIMING ANALYSIS (STA) CONSTRAINING DESIGN MULTIPLE CLOCK DOMAIN DESIGNS LOW POWER DESIGN RTL DESIGN FOR SOCS DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT. DIGITAL LOGIC DESIGN USING VERILOG / TARAATE, VAIBBHAV : 2016 ABSTRACT / INHALTSTEXT THIS BOOK IS DESIGNED TO SERVE AS A HANDS-ON PROFESSIONAL REFERENCE WITH ADDITIONAL UTILITY AS A TEXTBOOK FOR UPPER UNDERGRADUATE AND SOME GRADUATE COURSES IN DIGITAL LOGIC DESIGN. THIS BOOK IS ORGANIZED IN SUCH A WAY THAT THAT IT CAN DESCRIBE A NUMBER OF RTL DESIGN SCENARIOS, FROM SIMPLE TO COMPLEX. THE BOOK CONSTRUCTS THE LOGIC DESIGN STORY FROM THE FUNDAMENTALS OF LOGIC DESIGN TO ADVANCED RTL DESIGN CONCEPTS. KEEPING IN VIEW THE IMPORTANCE OF MINIATURIZATION TODAY, THE BOOK GIVES PRACTICAL INFORMATION ON THE ISSUES WITH ASIC RTL DESIGN AND HOW TO OVERCOME THESE CONCERNS. IT CLEARLY EXPLAINS HOW TO WRITE AN EFFICIENT RTL CODE AND HOW TO IMPROVE DESIGN PERFORMANCE. THE BOOK ALSO DESCRIBES ADVANCED RTL DESIGN CONCEPTS SUCH AS LOW-POWER DESIGN, MULTIPLE CLOCK-DOMAIN DESIGN, AND SOC-BASED DESIGN. THE PRACTICAL ORIENTATION OF THE BOOK MAKES IT IDEAL FOR TRAINING PROGRAMS FOR PRACTICING DESIGN ENGINEERS AND FOR SHORT-TERM VOCATIONAL PROGRAMS. THE CONTENTS OF THE BOOK WILL ALSO MAKE IT A USEFUL READ FOR STUDENTS AND HOBBYISTS. DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
any_adam_object	1
author	Taraate, Vaibbhav
author_facet	Taraate, Vaibbhav
author_role	aut
author_sort	Taraate, Vaibbhav
author_variant	v t vt
building	Verbundindex
bvnumber	BV043579778
collection	ZDB-2-ENG
ctrlnum	(ZDB-2-ENG)978-81-322-2791-5 (OCoLC)951067989 (DE-599)BVBBV043579778
dewey-full	621.3815
dewey-hundreds	600 - Technology (Applied sciences)
dewey-ones	621 - Applied physics
dewey-raw	621.3815
dewey-search	621.3815
dewey-sort	3621.3815
dewey-tens	620 - Engineering and allied operations
discipline	Elektrotechnik / Elektronik / Nachrichtentechnik
doi_str_mv	10.1007/978-81-322-2791-5
format	Electronic eBook
fullrecord	<?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03225nmm a2200625zc 4500</leader><controlfield tag="001">BV043579778</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20160816 </controlfield><controlfield tag="007">cr\|uuu---uuuuu</controlfield><controlfield tag="008">160601s2016 \|\|\|\| o\|\|u\| \|\|\|\|\|\|eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9788132227915</subfield><subfield code="c">Online</subfield><subfield code="9">978-81-322-2791-5</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-81-322-2791-5</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-2-ENG)978-81-322-2791-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)951067989</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV043579778</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-706</subfield><subfield code="a">DE-1046</subfield><subfield code="a">DE-1043</subfield><subfield code="a">DE-Aug4</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-861</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-859</subfield><subfield code="a">DE-863</subfield><subfield code="a">DE-634</subfield><subfield code="a">DE-862</subfield><subfield code="a">DE-92</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Taraate, Vaibbhav</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Digital logic design using verilog</subfield><subfield code="b">coding and RTL synthesis</subfield><subfield code="c">Vaibbhav Taraate</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">[New Delhi]</subfield><subfield code="b">Springer</subfield><subfield code="c">[2016]</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">© 2016</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (XXIII, 416 p. 267 illus., 226 illus. in color)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Microelectronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronic circuits</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics and Microelectronics, Instrumentation</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Logic Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Ingenieurwissenschaften</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druckausgabe</subfield><subfield code="z">978-81-322-2789-2</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Springer Fremddatenuebernahme</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=028994450&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Springer Fremddatenuebernahme</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=028994450&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Abstract</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-2-ENG_2016</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-028994450</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FAB01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FAW01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FHA01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FHR01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FKE01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FRO01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FWS01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">FWS02</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-81-322-2791-5</subfield><subfield code="l">UBY01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection>
id	DE-604.BV043579778
illustrated	Not Illustrated
indexdate	2025-02-20T06:53:09Z
institution	BVB
isbn	9788132227915
language	English
oai_aleph_id	oai:aleph.bib-bvb.de:BVB01-028994450
oclc_num	951067989
open_access_boolean
owner	DE-706 DE-1046 DE-1043 DE-Aug4 DE-898 DE-BY-UBR DE-861 DE-573 DE-859 DE-863 DE-BY-FWS DE-634 DE-862 DE-BY-FWS DE-92
owner_facet	DE-706 DE-1046 DE-1043 DE-Aug4 DE-898 DE-BY-UBR DE-861 DE-573 DE-859 DE-863 DE-BY-FWS DE-634 DE-862 DE-BY-FWS DE-92
physical	1 Online-Ressource (XXIII, 416 p. 267 illus., 226 illus. in color)
psigel	ZDB-2-ENG ZDB-2-ENG_2016
publishDate	2016
publishDateSearch	2016
publishDateSort	2016
publisher	Springer
record_format	marc
spellingShingle	Taraate, Vaibbhav Digital logic design using verilog coding and RTL synthesis Engineering Logic design Electronics Microelectronics Electronic circuits Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Ingenieurwissenschaften
title	Digital logic design using verilog coding and RTL synthesis
title_auth	Digital logic design using verilog coding and RTL synthesis
title_exact_search	Digital logic design using verilog coding and RTL synthesis
title_full	Digital logic design using verilog coding and RTL synthesis Vaibbhav Taraate
title_fullStr	Digital logic design using verilog coding and RTL synthesis Vaibbhav Taraate
title_full_unstemmed	Digital logic design using verilog coding and RTL synthesis Vaibbhav Taraate
title_short	Digital logic design using verilog
title_sort	digital logic design using verilog coding and rtl synthesis
title_sub	coding and RTL synthesis
topic	Engineering Logic design Electronics Microelectronics Electronic circuits Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Ingenieurwissenschaften
topic_facet	Engineering Logic design Electronics Microelectronics Electronic circuits Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Ingenieurwissenschaften
url	https://doi.org/10.1007/978-81-322-2791-5 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=028994450&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=028994450&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA
work_keys_str_mv	AT taraatevaibbhav digitallogicdesignusingverilogcodingandrtlsynthesis

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