Digital logic design using verilog: coding and RTL synthesis
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
[New Delhi]
Springer
[2016]
|
| Schlagworte: | |
| Online-Zugang: | BTU01 FAB01 FAW01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 URL des Erstveröffentlichers Inhaltsverzeichnis Abstract |
| Beschreibung: | 1 Online-Ressource (XXIII, 416 p. 267 illus., 226 illus. in color) |
| ISBN: | 9788132227915 |
| DOI: | 10.1007/978-81-322-2791-5 |
Internformat
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Datensatz im Suchindex
| DE-BY-FWS_katkey | 618901 |
|---|---|
| _version_ | 1824554524951445504 |
| adam_text | DIGITAL LOGIC DESIGN USING VERILOG
/ TARAATE, VAIBBHAV
: 2016
TABLE OF CONTENTS / INHALTSVERZEICHNIS
INTRODUCTION
COMBINATIONAL LOGIC DESIGN (PART I)
COMBINATIONAL LOGIC DESIGN (PART II)
COMBINATIONAL DESIGN GUIDELINES
SEQUENTIAL LOGIC DESIGN
SEQUENTIAL DESIGN GUIDELINES
COMPLEX DESIGNS USING VERILOG RTL
FINITE STATE MACHINES
SIMULATION CONCEPTS AND PLD BASED DESIGNS
RTL SYNTHESIS
STATIC TIMING ANALYSIS (STA)
CONSTRAINING DESIGN
MULTIPLE CLOCK DOMAIN DESIGNS
LOW POWER DESIGN
RTL DESIGN FOR SOCS
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
DIGITAL LOGIC DESIGN USING VERILOG
/ TARAATE, VAIBBHAV
: 2016
ABSTRACT / INHALTSTEXT
THIS BOOK IS DESIGNED TO SERVE AS A HANDS-ON PROFESSIONAL REFERENCE WITH
ADDITIONAL UTILITY AS A TEXTBOOK FOR UPPER UNDERGRADUATE AND SOME
GRADUATE COURSES IN DIGITAL LOGIC DESIGN. THIS BOOK IS ORGANIZED IN SUCH
A WAY THAT THAT IT CAN DESCRIBE A NUMBER OF RTL DESIGN SCENARIOS, FROM
SIMPLE TO COMPLEX. THE BOOK CONSTRUCTS THE LOGIC DESIGN STORY FROM THE
FUNDAMENTALS OF LOGIC DESIGN TO ADVANCED RTL DESIGN CONCEPTS. KEEPING IN
VIEW THE IMPORTANCE OF MINIATURIZATION TODAY, THE BOOK GIVES PRACTICAL
INFORMATION ON THE ISSUES WITH ASIC RTL DESIGN AND HOW TO OVERCOME THESE
CONCERNS. IT CLEARLY EXPLAINS HOW TO WRITE AN EFFICIENT RTL CODE AND HOW
TO IMPROVE DESIGN PERFORMANCE. THE BOOK ALSO DESCRIBES ADVANCED RTL
DESIGN CONCEPTS SUCH AS LOW-POWER DESIGN, MULTIPLE CLOCK-DOMAIN DESIGN,
AND SOC-BASED DESIGN. THE PRACTICAL ORIENTATION OF THE BOOK MAKES IT
IDEAL FOR TRAINING PROGRAMS FOR PRACTICING DESIGN ENGINEERS AND FOR
SHORT-TERM VOCATIONAL PROGRAMS. THE CONTENTS OF THE BOOK WILL ALSO MAKE
IT A USEFUL READ FOR STUDENTS AND HOBBYISTS.
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
|
| any_adam_object | 1 |
| author | Taraate, Vaibbhav |
| author_facet | Taraate, Vaibbhav |
| author_role | aut |
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-81-322-2791-5 |
| format | Electronic eBook |
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| id | DE-604.BV043579778 |
| illustrated | Not Illustrated |
| indexdate | 2025-02-20T06:53:09Z |
| institution | BVB |
| isbn | 9788132227915 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-028994450 |
| oclc_num | 951067989 |
| open_access_boolean | |
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| physical | 1 Online-Ressource (XXIII, 416 p. 267 illus., 226 illus. in color) |
| psigel | ZDB-2-ENG ZDB-2-ENG_2016 |
| publishDate | 2016 |
| publishDateSearch | 2016 |
| publishDateSort | 2016 |
| publisher | Springer |
| record_format | marc |
| spellingShingle | Taraate, Vaibbhav Digital logic design using verilog coding and RTL synthesis Engineering Logic design Electronics Microelectronics Electronic circuits Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Ingenieurwissenschaften |
| title | Digital logic design using verilog coding and RTL synthesis |
| title_auth | Digital logic design using verilog coding and RTL synthesis |
| title_exact_search | Digital logic design using verilog coding and RTL synthesis |
| title_full | Digital logic design using verilog coding and RTL synthesis Vaibbhav Taraate |
| title_fullStr | Digital logic design using verilog coding and RTL synthesis Vaibbhav Taraate |
| title_full_unstemmed | Digital logic design using verilog coding and RTL synthesis Vaibbhav Taraate |
| title_short | Digital logic design using verilog |
| title_sort | digital logic design using verilog coding and rtl synthesis |
| title_sub | coding and RTL synthesis |
| topic | Engineering Logic design Electronics Microelectronics Electronic circuits Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Ingenieurwissenschaften |
| topic_facet | Engineering Logic design Electronics Microelectronics Electronic circuits Circuits and Systems Electronics and Microelectronics, Instrumentation Logic Design Ingenieurwissenschaften |
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