Transient-induced latchup in CMOS integrated circuits:
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| Main Author: | |
|---|---|
| Format: | Electronic eBook |
| Language: | English |
| Published: |
[Piscataway, NJ]
IEEE Press
©2009
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| Subjects: | |
| Online Access: | FRO01 UBG01 FHI01 FHN01 Volltext |
| Item Description: | Includes bibliographical references and index "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description |
| Physical Description: | 1 Online-Ressource (xiii, 249 pages) |
| ISBN: | 9780470824085 0470824085 1282382187 9781282382183 9780470824092 0470824093 9780470824078 0470824077 |
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| indexdate | 2024-07-10T07:24:43Z |
| institution | BVB |
| isbn | 9780470824085 0470824085 1282382187 9781282382183 9780470824092 0470824093 9780470824078 0470824077 |
| language | English |
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| publisher | IEEE Press |
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| spelling | Ker, Ming-Dou Verfasser aut Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu [Piscataway, NJ] IEEE Press ©2009 1 Online-Ressource (xiii, 249 pages) txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description COMPUTERS / Logic Design bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh Metal oxide semiconductors, Complementary / Defects fast Metal oxide semiconductors, Complementary / Reliability fast Metal oxide semiconductors, Complementary / Defects Metal oxide semiconductors, Complementary / Reliability Hsu, Sheng-Fu Sonstige oth https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Ker, Ming-Dou Transient-induced latchup in CMOS integrated circuits COMPUTERS / Logic Design bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh Metal oxide semiconductors, Complementary / Defects fast Metal oxide semiconductors, Complementary / Reliability fast Metal oxide semiconductors, Complementary / Defects Metal oxide semiconductors, Complementary / Reliability |
| title | Transient-induced latchup in CMOS integrated circuits |
| title_auth | Transient-induced latchup in CMOS integrated circuits |
| title_exact_search | Transient-induced latchup in CMOS integrated circuits |
| title_full | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_fullStr | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_full_unstemmed | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_short | Transient-induced latchup in CMOS integrated circuits |
| title_sort | transient induced latchup in cmos integrated circuits |
| topic | COMPUTERS / Logic Design bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh Metal oxide semiconductors, Complementary / Defects fast Metal oxide semiconductors, Complementary / Reliability fast Metal oxide semiconductors, Complementary / Defects Metal oxide semiconductors, Complementary / Reliability |
| topic_facet | COMPUTERS / Logic Design TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. Metal oxide semiconductors, Complementary / Defects Metal oxide semiconductors, Complementary / Reliability |
| url | https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092 |
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