Transient-induced latchup in CMOS integrated circuits:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
[Piscataway, NJ]
IEEE Press
©2009
|
| Schlagworte: | |
| Online-Zugang: | FRO01 UBG01 FHI01 FHN01 Volltext |
| Beschreibung: | Includes bibliographical references and index "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description |
| Beschreibung: | 1 Online-Ressource (xiii, 249 pages) |
| ISBN: | 9780470824085 0470824085 1282382187 9781282382183 9780470824092 0470824093 9780470824078 0470824077 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV043392252 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 160222s2009 |||| o||u| ||||||eng d | ||
| 020 | |a 9780470824085 |c electronic bk. |9 978-0-470-82408-5 | ||
| 020 | |a 0470824085 |c electronic bk. |9 0-470-82408-5 | ||
| 020 | |a 1282382187 |9 1-282-38218-7 | ||
| 020 | |a 9781282382183 |9 978-1-282-38218-3 | ||
| 020 | |a 9780470824092 |9 978-0-470-82409-2 | ||
| 020 | |a 0470824093 |9 0-470-82409-3 | ||
| 020 | |a 9780470824078 |c HB |9 978-0-470-82407-8 | ||
| 020 | |a 0470824077 |c HB |9 0-470-82407-7 | ||
| 024 | 7 | |a 10.1002/9780470824092 |2 doi | |
| 035 | |a (ZDB-35-WIC)ocn669008259 | ||
| 035 | |a (OCoLC)669008259 | ||
| 035 | |a (DE-599)BVBBV043392252 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-861 |a DE-573 |a DE-92 | ||
| 082 | 0 | |a 621.39/5 |2 22 | |
| 100 | 1 | |a Ker, Ming-Dou |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Transient-induced latchup in CMOS integrated circuits |c Ming-Dou Ker and Sheng-Fu Hsu |
| 264 | 1 | |a [Piscataway, NJ] |b IEEE Press |c ©2009 | |
| 300 | |a 1 Online-Ressource (xiii, 249 pages) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Includes bibliographical references and index | ||
| 500 | |a "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description | ||
| 650 | 7 | |a COMPUTERS / Logic Design |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic |2 bisacsh | |
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. |2 bisacsh | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary / Defects |2 fast | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary / Reliability |2 fast | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary / Defects | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary / Reliability | |
| 700 | 1 | |a Hsu, Sheng-Fu |e Sonstige |4 oth | |
| 856 | 4 | 0 | |u https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092 |x Verlag |z URL des Erstveröffentlichers |3 Volltext |
| 912 | |a ZDB-35-WIC |a ZDB-35-WEL | ||
| 940 | 1 | |q UBG_PDA_WIC | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-028810836 | ||
| 966 | e | |u https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092 |l FRO01 |p ZDB-35-WIC |q FRO_PDA_WIC |x Verlag |3 Volltext | |
| 966 | e | |u https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092 |l UBG01 |p ZDB-35-WIC |q UBG_PDA_WIC |x Verlag |3 Volltext | |
| 966 | e | |u https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5453758 |l FHI01 |p ZDB-35-WEL |x Aggregator |3 Volltext | |
| 966 | e | |u https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5453758 |l FHN01 |p ZDB-35-WEL |x Aggregator |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804175968469778432 |
|---|---|
| any_adam_object | |
| author | Ker, Ming-Dou |
| author_facet | Ker, Ming-Dou |
| author_role | aut |
| author_sort | Ker, Ming-Dou |
| author_variant | m d k mdk |
| building | Verbundindex |
| bvnumber | BV043392252 |
| collection | ZDB-35-WIC ZDB-35-WEL |
| ctrlnum | (ZDB-35-WIC)ocn669008259 (OCoLC)669008259 (DE-599)BVBBV043392252 |
| dewey-full | 621.39/5 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/5 |
| dewey-search | 621.39/5 |
| dewey-sort | 3621.39 15 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03603nmm a2200577zc 4500</leader><controlfield tag="001">BV043392252</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">160222s2009 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470824085</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">978-0-470-82408-5</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0470824085</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">0-470-82408-5</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1282382187</subfield><subfield code="9">1-282-38218-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781282382183</subfield><subfield code="9">978-1-282-38218-3</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470824092</subfield><subfield code="9">978-0-470-82409-2</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0470824093</subfield><subfield code="9">0-470-82409-3</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780470824078</subfield><subfield code="c">HB</subfield><subfield code="9">978-0-470-82407-8</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0470824077</subfield><subfield code="c">HB</subfield><subfield code="9">0-470-82407-7</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1002/9780470824092</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(ZDB-35-WIC)ocn669008259</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)669008259</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV043392252</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-861</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-92</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/5</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Ker, Ming-Dou</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Transient-induced latchup in CMOS integrated circuits</subfield><subfield code="c">Ming-Dou Ker and Sheng-Fu Hsu</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">[Piscataway, NJ]</subfield><subfield code="b">IEEE Press</subfield><subfield code="c">©2009</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (xiii, 249 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">"Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COMPUTERS / Logic Design</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI.</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Metal oxide semiconductors, Complementary / Defects</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Metal oxide semiconductors, Complementary / Reliability</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metal oxide semiconductors, Complementary / Defects</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metal oxide semiconductors, Complementary / Reliability</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Hsu, Sheng-Fu</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092</subfield><subfield code="x">Verlag</subfield><subfield code="z">URL des Erstveröffentlichers</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-35-WIC</subfield><subfield code="a">ZDB-35-WEL</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">UBG_PDA_WIC</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-028810836</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092</subfield><subfield code="l">FRO01</subfield><subfield code="p">ZDB-35-WIC</subfield><subfield code="q">FRO_PDA_WIC</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092</subfield><subfield code="l">UBG01</subfield><subfield code="p">ZDB-35-WIC</subfield><subfield code="q">UBG_PDA_WIC</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5453758</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-35-WEL</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=5453758</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-35-WEL</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV043392252 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:24:43Z |
| institution | BVB |
| isbn | 9780470824085 0470824085 1282382187 9781282382183 9780470824092 0470824093 9780470824078 0470824077 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-028810836 |
| oclc_num | 669008259 |
| open_access_boolean | |
| owner | DE-861 DE-573 DE-92 |
| owner_facet | DE-861 DE-573 DE-92 |
| physical | 1 Online-Ressource (xiii, 249 pages) |
| psigel | ZDB-35-WIC ZDB-35-WEL UBG_PDA_WIC ZDB-35-WIC FRO_PDA_WIC ZDB-35-WIC UBG_PDA_WIC |
| publishDate | 2009 |
| publishDateSearch | 2009 |
| publishDateSort | 2009 |
| publisher | IEEE Press |
| record_format | marc |
| spelling | Ker, Ming-Dou Verfasser aut Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu [Piscataway, NJ] IEEE Press ©2009 1 Online-Ressource (xiii, 249 pages) txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description COMPUTERS / Logic Design bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh Metal oxide semiconductors, Complementary / Defects fast Metal oxide semiconductors, Complementary / Reliability fast Metal oxide semiconductors, Complementary / Defects Metal oxide semiconductors, Complementary / Reliability Hsu, Sheng-Fu Sonstige oth https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092 Verlag URL des Erstveröffentlichers Volltext |
| spellingShingle | Ker, Ming-Dou Transient-induced latchup in CMOS integrated circuits COMPUTERS / Logic Design bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh Metal oxide semiconductors, Complementary / Defects fast Metal oxide semiconductors, Complementary / Reliability fast Metal oxide semiconductors, Complementary / Defects Metal oxide semiconductors, Complementary / Reliability |
| title | Transient-induced latchup in CMOS integrated circuits |
| title_auth | Transient-induced latchup in CMOS integrated circuits |
| title_exact_search | Transient-induced latchup in CMOS integrated circuits |
| title_full | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_fullStr | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_full_unstemmed | Transient-induced latchup in CMOS integrated circuits Ming-Dou Ker and Sheng-Fu Hsu |
| title_short | Transient-induced latchup in CMOS integrated circuits |
| title_sort | transient induced latchup in cmos integrated circuits |
| topic | COMPUTERS / Logic Design bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh Metal oxide semiconductors, Complementary / Defects fast Metal oxide semiconductors, Complementary / Reliability fast Metal oxide semiconductors, Complementary / Defects Metal oxide semiconductors, Complementary / Reliability |
| topic_facet | COMPUTERS / Logic Design TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. Metal oxide semiconductors, Complementary / Defects Metal oxide semiconductors, Complementary / Reliability |
| url | https://onlinelibrary.wiley.com/doi/book/10.1002/9780470824092 |
| work_keys_str_mv | AT kermingdou transientinducedlatchupincmosintegratedcircuits AT hsushengfu transientinducedlatchupincmosintegratedcircuits |