APA (7th ed.) Citation

Bahukudumbi, S. (2010). Wafer-level testing and test during burn-in for integrated circuits. Artech House.

Chicago Style (17th ed.) Citation

Bahukudumbi, Sudarshan. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Boston: Artech House, 2010.

MLA (9th ed.) Citation

Bahukudumbi, Sudarshan. Wafer-level Testing and Test During Burn-in for Integrated Circuits. Artech House, 2010.

Warning: These citations may not always be 100% accurate.