Wafer-level testing and test during burn-in for integrated circuits:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston
Artech House
2010
|
| Schriftenreihe: | Artech House integrated microsystems series
|
| Schlagworte: | |
| Online-Zugang: | FAW01 FAW02 Volltext |
| Beschreibung: | Includes bibliographical references and index Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions |
| Beschreibung: | 1 Online-Ressource (xv, 198 p.) |
| ISBN: | 1596939893 1596939907 9781596939899 9781596939905 |
Internformat
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Datensatz im Suchindex
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| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
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| dewey-sort | 3621.381 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV043161868 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:19:23Z |
| institution | BVB |
| isbn | 1596939893 1596939907 9781596939899 9781596939905 |
| language | English |
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| physical | 1 Online-Ressource (xv, 198 p.) |
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| publishDate | 2010 |
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| publisher | Artech House |
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| series2 | Artech House integrated microsystems series |
| spelling | Bahukudumbi, Sudarshan Verfasser aut Wafer-level testing and test during burn-in for integrated circuits Sudarshan Bahukudumbi, Krishnendu Chakrabarty Boston Artech House 2010 1 Online-Ressource (xv, 198 p.) txt rdacontent c rdamedia cr rdacarrier Artech House integrated microsystems series Includes bibliographical references and index Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing Chakrabarty, Krishnendu Sonstige oth http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=339508 Aggregator Volltext |
| spellingShingle | Bahukudumbi, Sudarshan Wafer-level testing and test during burn-in for integrated circuits TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing |
| title | Wafer-level testing and test during burn-in for integrated circuits |
| title_auth | Wafer-level testing and test during burn-in for integrated circuits |
| title_exact_search | Wafer-level testing and test during burn-in for integrated circuits |
| title_full | Wafer-level testing and test during burn-in for integrated circuits Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| title_fullStr | Wafer-level testing and test during burn-in for integrated circuits Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| title_full_unstemmed | Wafer-level testing and test during burn-in for integrated circuits Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| title_short | Wafer-level testing and test during burn-in for integrated circuits |
| title_sort | wafer level testing and test during burn in for integrated circuits |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Microelectronics bisacsh TECHNOLOGY & ENGINEERING / Electronics / Digital bisacsh Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Microelectronics TECHNOLOGY & ENGINEERING / Electronics / Digital Integrated circuits Testing Integrated circuits Wafer-scale integration Semiconductors Testing |
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