Nano-CMOS circuit and physical design:
Gespeichert in:
| Format: | Elektronisch E-Book |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Hoboken, N.J.
John Wiley
©2005
|
| Schlagworte: | |
| Online-Zugang: | FAW01 FAW02 Volltext |
| Beschreibung: | Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002 Includes bibliographical references and index COVER -- TABLE OF CONTENTS -- FOREWORD -- PREFACE -- CHAPTER 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS -- 1.1 Design Methodology in the Nano-CMOS Era -- 1.2 Innovations Needed to Continue Performance Scaling -- 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography -- 1.3.1 Back-End-of-Line Challenges (Metallization) -- 1.3.2 Front-End-of-Line Challenges (Transistors) -- 1.4 Process Control and Reliability -- 1.5 Lithographic Issues and Mask Data Explosion -- 1.6 New Breed of Circuit and Physical Design Engineers -- 1.7 Modeling Challenges -- 1.8 Need for Design Methodology Changes -- 1.9 Summary -- References -- PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS -- CHAPTER 2 CMOS DEVICE AND PROCESS TECHNOLOGY -- 2.1 Equipment Requirements for Front-End Processing -- 2.2 Front-End-Device Problems in CMOS Scaling -- 2.3 Back-End-of-Line Technology -- References -- - CHAPTER 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY -- 3.1 Introduction and Simple Imaging Theory -- 3.2 Challenges for the 100-nm Node -- 3.3 Resolution Enhancement Techniques: Physics -- 3.4 Physical Design Style Impact on RET and OPC Complexity -- 3.5 The Road Ahead: Future Lithographic Technologies -- References -- PART II PROCESS SCALING IMPACT ON DESIGN -- CHAPTER 4 MIXED-SIGNAL CIRCUIT DESIGN -- 4.1 Introduction -- 4.2 Design Considerations -- 4.3 Device Modeling -- 4.4 Passive Components -- 4.5 Design Methodology -- 4.6 Low-Voltage Techniques -- 4.7 Design Procedures -- 4.8 Electrostatic Discharge Protection -- 4.9 Noise Isolation -- 4.10 Decoupling -- 4.11 Power Busing -- 4.12 Integration Problems -- 4.13 Summary -- References -- CHAPTER 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN -- 5.1 Introduction -- 5.2 ESD Standards and Models -- 5.3 ESD Protection Design -- 5.4 Low-C ESD Protection Design for High-Speed I/O -- - 5.5 ESD Protection Design for Mixed-Voltage I/O -- 5.6 SCR Devices for ESD Protection -- 5.7 Summary -- References -- CHAPTER 6 INPUT/OUTPUT DESIGN -- 6.1 Introduction -- 6.2 I/O Standards -- 6.3 Signal Transfer -- 6.4 ESD Protection -- 6.5 I/O Switching Noise -- 6.6 Termination -- 6.7 Impedance Matching -- 6.8 Preemphasis -- 6.9 Equalization -- 6.10 Conclusion -- References -- CHAPTER 7 DRAM -- 7.1 Introduction -- 7.2 DRAM Basics -- 7.3 Scaling the Capacitor -- 7.4 Scaling the Array Transistor -- 7.5 Scaling the Sense Amplifier -- 7.6 Summary -- References -- CHAPTER 8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS -- 8.1 Introduction -- 8.2 Interconnect Parasitics Extraction -- 8.3 Signal Integrity Analysis -- 8.4 Design Solutions for Signal Integrity -- 8.5 Summary -- References -- CHAPTER 9 ULTRALOW POWER CIRCUIT DESIGN -- 9.1 Introduction -- 9.2 Design-Time Low-Power Techniques -- 9.3 Run-Time Low-Power Techniques -- 9.4 Technology Innovations for Low-Power Design -- - 9.5 Perspectives for Future Ultralow-Power Design -- References -- PART III IMPA. Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation |
| Beschreibung: | 1 Online-Ressource (xviii, 393 pages) |
| ISBN: | 0471466107 0471678864 9780471466109 9780471678861 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV043138489 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 151126s2005 |||| o||u| ||||||eng d | ||
| 020 | |a 0471466107 |9 0-471-46610-7 | ||
| 020 | |a 0471678864 |c electronic bk. |9 0-471-67886-4 | ||
| 020 | |a 9780471466109 |9 978-0-471-46610-9 | ||
| 020 | |a 9780471678861 |c electronic bk. |9 978-0-471-67886-1 | ||
| 035 | |a (OCoLC)228136455 | ||
| 035 | |a (DE-599)BVBBV043138489 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-1046 |a DE-1047 | ||
| 082 | 0 | |a 621.39/732 |2 22 | |
| 245 | 1 | 0 | |a Nano-CMOS circuit and physical design |c Ban P. Wong [and others] |
| 264 | 1 | |a Hoboken, N.J. |b John Wiley |c ©2005 | |
| 300 | |a 1 Online-Ressource (xviii, 393 pages) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002 | ||
| 500 | |a Includes bibliographical references and index | ||
| 500 | |a COVER -- TABLE OF CONTENTS -- FOREWORD -- PREFACE -- CHAPTER 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS -- 1.1 Design Methodology in the Nano-CMOS Era -- 1.2 Innovations Needed to Continue Performance Scaling -- 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography -- 1.3.1 Back-End-of-Line Challenges (Metallization) -- 1.3.2 Front-End-of-Line Challenges (Transistors) -- 1.4 Process Control and Reliability -- 1.5 Lithographic Issues and Mask Data Explosion -- 1.6 New Breed of Circuit and Physical Design Engineers -- 1.7 Modeling Challenges -- 1.8 Need for Design Methodology Changes -- 1.9 Summary -- References -- PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS -- CHAPTER 2 CMOS DEVICE AND PROCESS TECHNOLOGY -- 2.1 Equipment Requirements for Front-End Processing -- 2.2 Front-End-Device Problems in CMOS Scaling -- 2.3 Back-End-of-Line Technology -- References -- | ||
| 500 | |a - CHAPTER 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY -- 3.1 Introduction and Simple Imaging Theory -- 3.2 Challenges for the 100-nm Node -- 3.3 Resolution Enhancement Techniques: Physics -- 3.4 Physical Design Style Impact on RET and OPC Complexity -- 3.5 The Road Ahead: Future Lithographic Technologies -- References -- PART II PROCESS SCALING IMPACT ON DESIGN -- CHAPTER 4 MIXED-SIGNAL CIRCUIT DESIGN -- 4.1 Introduction -- 4.2 Design Considerations -- 4.3 Device Modeling -- 4.4 Passive Components -- 4.5 Design Methodology -- 4.6 Low-Voltage Techniques -- 4.7 Design Procedures -- 4.8 Electrostatic Discharge Protection -- 4.9 Noise Isolation -- 4.10 Decoupling -- 4.11 Power Busing -- 4.12 Integration Problems -- 4.13 Summary -- References -- CHAPTER 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN -- 5.1 Introduction -- 5.2 ESD Standards and Models -- 5.3 ESD Protection Design -- 5.4 Low-C ESD Protection Design for High-Speed I/O -- | ||
| 500 | |a - 5.5 ESD Protection Design for Mixed-Voltage I/O -- 5.6 SCR Devices for ESD Protection -- 5.7 Summary -- References -- CHAPTER 6 INPUT/OUTPUT DESIGN -- 6.1 Introduction -- 6.2 I/O Standards -- 6.3 Signal Transfer -- 6.4 ESD Protection -- 6.5 I/O Switching Noise -- 6.6 Termination -- 6.7 Impedance Matching -- 6.8 Preemphasis -- 6.9 Equalization -- 6.10 Conclusion -- References -- CHAPTER 7 DRAM -- 7.1 Introduction -- 7.2 DRAM Basics -- 7.3 Scaling the Capacitor -- 7.4 Scaling the Array Transistor -- 7.5 Scaling the Sense Amplifier -- 7.6 Summary -- References -- CHAPTER 8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS -- 8.1 Introduction -- 8.2 Interconnect Parasitics Extraction -- 8.3 Signal Integrity Analysis -- 8.4 Design Solutions for Signal Integrity -- 8.5 Summary -- References -- CHAPTER 9 ULTRALOW POWER CIRCUIT DESIGN -- 9.1 Introduction -- 9.2 Design-Time Low-Power Techniques -- 9.3 Run-Time Low-Power Techniques -- 9.4 Technology Innovations for Low-Power Design -- | ||
| 500 | |a - 9.5 Perspectives for Future Ultralow-Power Design -- References -- PART III IMPA. | ||
| 500 | |a Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation | ||
| 650 | 7 | |a COMPUTERS / Machine Theory |2 bisacsh | |
| 650 | 7 | |a COMPUTERS / Computer Engineering |2 bisacsh | |
| 650 | 7 | |a COMPUTERS / Hardware / General |2 bisacsh | |
| 650 | 7 | |a Integrated circuits / Design and construction |2 fast | |
| 650 | 7 | |a Metal oxide semiconductors, Complementary / Design and construction |2 fast | |
| 650 | 7 | |a Circuit intégré |2 rasuqam | |
| 650 | 7 | |a CMOS (Circuit intégré) |2 rasuqam | |
| 650 | 7 | |a Conception technique |2 rasuqam | |
| 650 | 7 | |a Nanotechnologie |2 rasuqam | |
| 650 | 7 | |a MOS complémentaires / Conception et construction |2 ram | |
| 650 | 7 | |a Circuits intégrés |2 ram | |
| 650 | 7 | |a CMOS-Schaltung |2 swd | |
| 650 | 7 | |a Nanotechnologie |2 swd | |
| 650 | 7 | |a Layout <Mikroelektronik> |2 swd | |
| 650 | 4 | |a Metal oxide semiconductors, Complementary |x Design and construction | |
| 650 | 4 | |a Integrated circuits |x Design and construction | |
| 700 | 1 | |a Wong, Ban P. |e Sonstige |4 oth | |
| 856 | 4 | 0 | |u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=130966 |x Aggregator |3 Volltext |
| 912 | |a ZDB-4-EBA | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-028562680 | ||
| 966 | e | |u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=130966 |l FAW01 |p ZDB-4-EBA |q FAW_PDA_EBA |x Aggregator |3 Volltext | |
| 966 | e | |u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=130966 |l FAW02 |p ZDB-4-EBA |q FAW_PDA_EBA |x Aggregator |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804175585137655808 |
|---|---|
| any_adam_object | |
| building | Verbundindex |
| bvnumber | BV043138489 |
| collection | ZDB-4-EBA |
| ctrlnum | (OCoLC)228136455 (DE-599)BVBBV043138489 |
| dewey-full | 621.39/732 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/732 |
| dewey-search | 621.39/732 |
| dewey-sort | 3621.39 3732 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>06149nmm a2200625zc 4500</leader><controlfield tag="001">BV043138489</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">151126s2005 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0471466107</subfield><subfield code="9">0-471-46610-7</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0471678864</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">0-471-67886-4</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780471466109</subfield><subfield code="9">978-0-471-46610-9</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780471678861</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">978-0-471-67886-1</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)228136455</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV043138489</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-1046</subfield><subfield code="a">DE-1047</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/732</subfield><subfield code="2">22</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Nano-CMOS circuit and physical design</subfield><subfield code="c">Ban P. Wong [and others]</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Hoboken, N.J.</subfield><subfield code="b">John Wiley</subfield><subfield code="c">©2005</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (xviii, 393 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">COVER -- TABLE OF CONTENTS -- FOREWORD -- PREFACE -- CHAPTER 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS -- 1.1 Design Methodology in the Nano-CMOS Era -- 1.2 Innovations Needed to Continue Performance Scaling -- 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography -- 1.3.1 Back-End-of-Line Challenges (Metallization) -- 1.3.2 Front-End-of-Line Challenges (Transistors) -- 1.4 Process Control and Reliability -- 1.5 Lithographic Issues and Mask Data Explosion -- 1.6 New Breed of Circuit and Physical Design Engineers -- 1.7 Modeling Challenges -- 1.8 Need for Design Methodology Changes -- 1.9 Summary -- References -- PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS -- CHAPTER 2 CMOS DEVICE AND PROCESS TECHNOLOGY -- 2.1 Equipment Requirements for Front-End Processing -- 2.2 Front-End-Device Problems in CMOS Scaling -- 2.3 Back-End-of-Line Technology -- References -- </subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a"> - CHAPTER 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY -- 3.1 Introduction and Simple Imaging Theory -- 3.2 Challenges for the 100-nm Node -- 3.3 Resolution Enhancement Techniques: Physics -- 3.4 Physical Design Style Impact on RET and OPC Complexity -- 3.5 The Road Ahead: Future Lithographic Technologies -- References -- PART II PROCESS SCALING IMPACT ON DESIGN -- CHAPTER 4 MIXED-SIGNAL CIRCUIT DESIGN -- 4.1 Introduction -- 4.2 Design Considerations -- 4.3 Device Modeling -- 4.4 Passive Components -- 4.5 Design Methodology -- 4.6 Low-Voltage Techniques -- 4.7 Design Procedures -- 4.8 Electrostatic Discharge Protection -- 4.9 Noise Isolation -- 4.10 Decoupling -- 4.11 Power Busing -- 4.12 Integration Problems -- 4.13 Summary -- References -- CHAPTER 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN -- 5.1 Introduction -- 5.2 ESD Standards and Models -- 5.3 ESD Protection Design -- 5.4 Low-C ESD Protection Design for High-Speed I/O -- </subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a"> - 5.5 ESD Protection Design for Mixed-Voltage I/O -- 5.6 SCR Devices for ESD Protection -- 5.7 Summary -- References -- CHAPTER 6 INPUT/OUTPUT DESIGN -- 6.1 Introduction -- 6.2 I/O Standards -- 6.3 Signal Transfer -- 6.4 ESD Protection -- 6.5 I/O Switching Noise -- 6.6 Termination -- 6.7 Impedance Matching -- 6.8 Preemphasis -- 6.9 Equalization -- 6.10 Conclusion -- References -- CHAPTER 7 DRAM -- 7.1 Introduction -- 7.2 DRAM Basics -- 7.3 Scaling the Capacitor -- 7.4 Scaling the Array Transistor -- 7.5 Scaling the Sense Amplifier -- 7.6 Summary -- References -- CHAPTER 8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS -- 8.1 Introduction -- 8.2 Interconnect Parasitics Extraction -- 8.3 Signal Integrity Analysis -- 8.4 Design Solutions for Signal Integrity -- 8.5 Summary -- References -- CHAPTER 9 ULTRALOW POWER CIRCUIT DESIGN -- 9.1 Introduction -- 9.2 Design-Time Low-Power Techniques -- 9.3 Run-Time Low-Power Techniques -- 9.4 Technology Innovations for Low-Power Design -- </subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a"> - 9.5 Perspectives for Future Ultralow-Power Design -- References -- PART III IMPA.</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COMPUTERS / Machine Theory</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COMPUTERS / Computer Engineering</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">COMPUTERS / Hardware / General</subfield><subfield code="2">bisacsh</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Integrated circuits / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Metal oxide semiconductors, Complementary / Design and construction</subfield><subfield code="2">fast</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Circuit intégré</subfield><subfield code="2">rasuqam</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">CMOS (Circuit intégré)</subfield><subfield code="2">rasuqam</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Conception technique</subfield><subfield code="2">rasuqam</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Nanotechnologie</subfield><subfield code="2">rasuqam</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">MOS complémentaires / Conception et construction</subfield><subfield code="2">ram</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Circuits intégrés</subfield><subfield code="2">ram</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">CMOS-Schaltung</subfield><subfield code="2">swd</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Nanotechnologie</subfield><subfield code="2">swd</subfield></datafield><datafield tag="650" ind1=" " ind2="7"><subfield code="a">Layout <Mikroelektronik></subfield><subfield code="2">swd</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Metal oxide semiconductors, Complementary</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits</subfield><subfield code="x">Design and construction</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Wong, Ban P.</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=130966</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-4-EBA</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-028562680</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=130966</subfield><subfield code="l">FAW01</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FAW_PDA_EBA</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=130966</subfield><subfield code="l">FAW02</subfield><subfield code="p">ZDB-4-EBA</subfield><subfield code="q">FAW_PDA_EBA</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV043138489 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:18:37Z |
| institution | BVB |
| isbn | 0471466107 0471678864 9780471466109 9780471678861 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-028562680 |
| oclc_num | 228136455 |
| open_access_boolean | |
| owner | DE-1046 DE-1047 |
| owner_facet | DE-1046 DE-1047 |
| physical | 1 Online-Ressource (xviii, 393 pages) |
| psigel | ZDB-4-EBA ZDB-4-EBA FAW_PDA_EBA |
| publishDate | 2005 |
| publishDateSearch | 2005 |
| publishDateSort | 2005 |
| publisher | John Wiley |
| record_format | marc |
| spelling | Nano-CMOS circuit and physical design Ban P. Wong [and others] Hoboken, N.J. John Wiley ©2005 1 Online-Ressource (xviii, 393 pages) txt rdacontent c rdamedia cr rdacarrier Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002 Includes bibliographical references and index COVER -- TABLE OF CONTENTS -- FOREWORD -- PREFACE -- CHAPTER 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS -- 1.1 Design Methodology in the Nano-CMOS Era -- 1.2 Innovations Needed to Continue Performance Scaling -- 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography -- 1.3.1 Back-End-of-Line Challenges (Metallization) -- 1.3.2 Front-End-of-Line Challenges (Transistors) -- 1.4 Process Control and Reliability -- 1.5 Lithographic Issues and Mask Data Explosion -- 1.6 New Breed of Circuit and Physical Design Engineers -- 1.7 Modeling Challenges -- 1.8 Need for Design Methodology Changes -- 1.9 Summary -- References -- PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS -- CHAPTER 2 CMOS DEVICE AND PROCESS TECHNOLOGY -- 2.1 Equipment Requirements for Front-End Processing -- 2.2 Front-End-Device Problems in CMOS Scaling -- 2.3 Back-End-of-Line Technology -- References -- - CHAPTER 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY -- 3.1 Introduction and Simple Imaging Theory -- 3.2 Challenges for the 100-nm Node -- 3.3 Resolution Enhancement Techniques: Physics -- 3.4 Physical Design Style Impact on RET and OPC Complexity -- 3.5 The Road Ahead: Future Lithographic Technologies -- References -- PART II PROCESS SCALING IMPACT ON DESIGN -- CHAPTER 4 MIXED-SIGNAL CIRCUIT DESIGN -- 4.1 Introduction -- 4.2 Design Considerations -- 4.3 Device Modeling -- 4.4 Passive Components -- 4.5 Design Methodology -- 4.6 Low-Voltage Techniques -- 4.7 Design Procedures -- 4.8 Electrostatic Discharge Protection -- 4.9 Noise Isolation -- 4.10 Decoupling -- 4.11 Power Busing -- 4.12 Integration Problems -- 4.13 Summary -- References -- CHAPTER 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN -- 5.1 Introduction -- 5.2 ESD Standards and Models -- 5.3 ESD Protection Design -- 5.4 Low-C ESD Protection Design for High-Speed I/O -- - 5.5 ESD Protection Design for Mixed-Voltage I/O -- 5.6 SCR Devices for ESD Protection -- 5.7 Summary -- References -- CHAPTER 6 INPUT/OUTPUT DESIGN -- 6.1 Introduction -- 6.2 I/O Standards -- 6.3 Signal Transfer -- 6.4 ESD Protection -- 6.5 I/O Switching Noise -- 6.6 Termination -- 6.7 Impedance Matching -- 6.8 Preemphasis -- 6.9 Equalization -- 6.10 Conclusion -- References -- CHAPTER 7 DRAM -- 7.1 Introduction -- 7.2 DRAM Basics -- 7.3 Scaling the Capacitor -- 7.4 Scaling the Array Transistor -- 7.5 Scaling the Sense Amplifier -- 7.6 Summary -- References -- CHAPTER 8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS -- 8.1 Introduction -- 8.2 Interconnect Parasitics Extraction -- 8.3 Signal Integrity Analysis -- 8.4 Design Solutions for Signal Integrity -- 8.5 Summary -- References -- CHAPTER 9 ULTRALOW POWER CIRCUIT DESIGN -- 9.1 Introduction -- 9.2 Design-Time Low-Power Techniques -- 9.3 Run-Time Low-Power Techniques -- 9.4 Technology Innovations for Low-Power Design -- - 9.5 Perspectives for Future Ultralow-Power Design -- References -- PART III IMPA. Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength optical lithography; impact of process scaling on circuit and physical implementation and low power with leaky transistors; and DFM, yield, and the impact of physical implementation COMPUTERS / Machine Theory bisacsh COMPUTERS / Computer Engineering bisacsh COMPUTERS / Hardware / General bisacsh Integrated circuits / Design and construction fast Metal oxide semiconductors, Complementary / Design and construction fast Circuit intégré rasuqam CMOS (Circuit intégré) rasuqam Conception technique rasuqam Nanotechnologie rasuqam MOS complémentaires / Conception et construction ram Circuits intégrés ram CMOS-Schaltung swd Nanotechnologie swd Layout <Mikroelektronik> swd Metal oxide semiconductors, Complementary Design and construction Integrated circuits Design and construction Wong, Ban P. Sonstige oth http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=130966 Aggregator Volltext |
| spellingShingle | Nano-CMOS circuit and physical design COMPUTERS / Machine Theory bisacsh COMPUTERS / Computer Engineering bisacsh COMPUTERS / Hardware / General bisacsh Integrated circuits / Design and construction fast Metal oxide semiconductors, Complementary / Design and construction fast Circuit intégré rasuqam CMOS (Circuit intégré) rasuqam Conception technique rasuqam Nanotechnologie rasuqam MOS complémentaires / Conception et construction ram Circuits intégrés ram CMOS-Schaltung swd Nanotechnologie swd Layout <Mikroelektronik> swd Metal oxide semiconductors, Complementary Design and construction Integrated circuits Design and construction |
| title | Nano-CMOS circuit and physical design |
| title_auth | Nano-CMOS circuit and physical design |
| title_exact_search | Nano-CMOS circuit and physical design |
| title_full | Nano-CMOS circuit and physical design Ban P. Wong [and others] |
| title_fullStr | Nano-CMOS circuit and physical design Ban P. Wong [and others] |
| title_full_unstemmed | Nano-CMOS circuit and physical design Ban P. Wong [and others] |
| title_short | Nano-CMOS circuit and physical design |
| title_sort | nano cmos circuit and physical design |
| topic | COMPUTERS / Machine Theory bisacsh COMPUTERS / Computer Engineering bisacsh COMPUTERS / Hardware / General bisacsh Integrated circuits / Design and construction fast Metal oxide semiconductors, Complementary / Design and construction fast Circuit intégré rasuqam CMOS (Circuit intégré) rasuqam Conception technique rasuqam Nanotechnologie rasuqam MOS complémentaires / Conception et construction ram Circuits intégrés ram CMOS-Schaltung swd Nanotechnologie swd Layout <Mikroelektronik> swd Metal oxide semiconductors, Complementary Design and construction Integrated circuits Design and construction |
| topic_facet | COMPUTERS / Machine Theory COMPUTERS / Computer Engineering COMPUTERS / Hardware / General Integrated circuits / Design and construction Metal oxide semiconductors, Complementary / Design and construction Circuit intégré CMOS (Circuit intégré) Conception technique Nanotechnologie MOS complémentaires / Conception et construction Circuits intégrés CMOS-Schaltung Layout <Mikroelektronik> Metal oxide semiconductors, Complementary Design and construction Integrated circuits Design and construction |
| url | http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=130966 |
| work_keys_str_mv | AT wongbanp nanocmoscircuitandphysicaldesign |