ASIC and FPGA verification: a guide to component modeling
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
San Francisco, Calif.
Morgan Kaufmann
© 2005
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Online-Zugang: | FAW01 FAW02 Volltext |
| Beschreibung: | Includes index 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification |
| Beschreibung: | 1 Online-Ressource (1 volume) |
| ISBN: | 0080475922 0125105819 1417549718 9780080475929 9780125105811 9781417549719 |
Internformat
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Datensatz im Suchindex
| _version_ | 1804175505469997056 |
|---|---|
| any_adam_object | |
| author | Munden, Richard |
| author_facet | Munden, Richard |
| author_role | aut |
| author_sort | Munden, Richard |
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| bvnumber | BV043098194 |
| collection | ZDB-4-EBA |
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| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
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| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV043098194 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:17:21Z |
| institution | BVB |
| isbn | 0080475922 0125105819 1417549718 9780080475929 9780125105811 9781417549719 |
| language | English |
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| physical | 1 Online-Ressource (1 volume) |
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| publishDate | 2005 |
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| spelling | Munden, Richard Verfasser aut ASIC and FPGA verification a guide to component modeling Richard Munden San Francisco, Calif. Morgan Kaufmann © 2005 1 Online-Ressource (1 volume) txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes index 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Application-specific integrated circuits fast Circuits intégrés à la demande Réseaux logiques programmables par l'utilisateur Application specific integrated circuits cct Application-specific integrated circuits Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Hierarchische Simulation (DE-588)4426470-7 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Verifikation (DE-588)4135577-5 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s Field programmable gate array (DE-588)4347749-5 s Hierarchische Simulation (DE-588)4426470-7 s 1\p DE-604 Digitalelektronik (DE-588)4260328-6 s Integrierte Schaltung (DE-588)4027242-4 s Verifikation (DE-588)4135577-5 s 2\p DE-604 http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=117163 Aggregator Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Munden, Richard ASIC and FPGA verification a guide to component modeling TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Application-specific integrated circuits fast Circuits intégrés à la demande Réseaux logiques programmables par l'utilisateur Application specific integrated circuits cct Application-specific integrated circuits Kundenspezifische Schaltung (DE-588)4122250-7 gnd Hierarchische Simulation (DE-588)4426470-7 gnd Digitalelektronik (DE-588)4260328-6 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Verifikation (DE-588)4135577-5 gnd Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4122250-7 (DE-588)4426470-7 (DE-588)4260328-6 (DE-588)4027242-4 (DE-588)4135577-5 (DE-588)4347749-5 |
| title | ASIC and FPGA verification a guide to component modeling |
| title_auth | ASIC and FPGA verification a guide to component modeling |
| title_exact_search | ASIC and FPGA verification a guide to component modeling |
| title_full | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_fullStr | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_full_unstemmed | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_short | ASIC and FPGA verification |
| title_sort | asic and fpga verification a guide to component modeling |
| title_sub | a guide to component modeling |
| topic | TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Application-specific integrated circuits fast Circuits intégrés à la demande Réseaux logiques programmables par l'utilisateur Application specific integrated circuits cct Application-specific integrated circuits Kundenspezifische Schaltung (DE-588)4122250-7 gnd Hierarchische Simulation (DE-588)4426470-7 gnd Digitalelektronik (DE-588)4260328-6 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Verifikation (DE-588)4135577-5 gnd Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic COMPUTERS / Logic Design Application-specific integrated circuits Circuits intégrés à la demande Réseaux logiques programmables par l'utilisateur Application specific integrated circuits Kundenspezifische Schaltung Hierarchische Simulation Digitalelektronik Integrierte Schaltung Verifikation Field programmable gate array |
| url | http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=117163 |
| work_keys_str_mv | AT mundenrichard asicandfpgaverificationaguidetocomponentmodeling |