Computer architecture: a quantitative approach
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Elsevier/Morgan Kaufmann Publishers
© 2007
|
| Ausgabe: | 4th ed |
| Schlagworte: | |
| Online-Zugang: | FAW01 FAW02 Volltext |
| Beschreibung: | Includes bibliographical references and index Fundamentals of computer design -- Instruction-level parallelism and its exploitation -- Limits on instruction-level parallelism -- Multiprocessors and thread-level parallelism -- Memory hierarchy design -- Storage systems -- Pipelining: basic and intermediate concepts -- Instruction set principles and examples -- Review of memory hierarchy The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability |
| Beschreibung: | 1 Online-Ressource (1 volume (various pagings)) |
| ISBN: | 0080475027 9780080475028 |
Internformat
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| 500 | |a Includes bibliographical references and index | ||
| 500 | |a Fundamentals of computer design -- Instruction-level parallelism and its exploitation -- Limits on instruction-level parallelism -- Multiprocessors and thread-level parallelism -- Memory hierarchy design -- Storage systems -- Pipelining: basic and intermediate concepts -- Instruction set principles and examples -- Review of memory hierarchy | ||
| 500 | |a The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability | ||
| 650 | 4 | |a Ordinateurs / Architecture | |
| 650 | 4 | |a Ordinateurs / Mémoires | |
| 650 | 4 | |a Parallélisme (Informatique) | |
| 650 | 4 | |a Systèmes enfouis (Informatique) / Conception et construction | |
| 650 | 4 | |a Réseaux d'ordinateurs | |
| 650 | 4 | |a Hiérarchie de mémoires (Informatique) | |
| 650 | 4 | |a Multiprocesseurs | |
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Datensatz im Suchindex
| _version_ | 1804175454223990784 |
|---|---|
| any_adam_object | |
| author | Hennessy, John L. 1952- |
| author_GND | (DE-588)114326436 (DE-588)114326452 (DE-588)1154327930 |
| author_facet | Hennessy, John L. 1952- |
| author_role | aut |
| author_sort | Hennessy, John L. 1952- |
| author_variant | j l h jl jlh |
| building | Verbundindex |
| bvnumber | BV043070941 |
| classification_rvk | ST 150 |
| collection | ZDB-4-EBA |
| ctrlnum | (OCoLC)145556090 (DE-599)BVBBV043070941 |
| dewey-full | 004.2/2 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004.2/2 |
| dewey-search | 004.2/2 |
| dewey-sort | 14.2 12 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik |
| edition | 4th ed |
| format | Electronic eBook |
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| id | DE-604.BV043070941 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:16:32Z |
| institution | BVB |
| isbn | 0080475027 9780080475028 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-028495132 |
| oclc_num | 145556090 |
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| owner | DE-1046 DE-1047 |
| owner_facet | DE-1046 DE-1047 |
| physical | 1 Online-Ressource (1 volume (various pagings)) |
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| publishDate | 2007 |
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| publisher | Elsevier/Morgan Kaufmann Publishers |
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| spelling | Hennessy, John L. 1952- Verfasser (DE-588)114326436 aut Computer architecture a quantitative approach John L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau [and others] 4th ed Amsterdam Elsevier/Morgan Kaufmann Publishers © 2007 1 Online-Ressource (1 volume (various pagings)) txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index Fundamentals of computer design -- Instruction-level parallelism and its exploitation -- Limits on instruction-level parallelism -- Multiprocessors and thread-level parallelism -- Memory hierarchy design -- Storage systems -- Pipelining: basic and intermediate concepts -- Instruction set principles and examples -- Review of memory hierarchy The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors--chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability Ordinateurs / Architecture Ordinateurs / Mémoires Parallélisme (Informatique) Systèmes enfouis (Informatique) / Conception et construction Réseaux d'ordinateurs Hiérarchie de mémoires (Informatique) Multiprocesseurs Arithmétique interne des ordinateurs COMPUTERS / Systems Architecture / General bisacsh Computer architecture fast Arquitetura e organização de computadores larpcal Architektur Computer architecture Konstruktion (DE-588)4032231-2 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Computerarchitektur (DE-588)4048717-9 s 1\p DE-604 Konstruktion (DE-588)4032231-2 s 2\p DE-604 Patterson, David A. 1947- Sonstige (DE-588)114326452 oth Arpaci-Dusseau, Andrea C. Sonstige (DE-588)1154327930 oth Erscheint auch als Druck-Ausgabe, Paperback 0-12-370490-1 Erscheint auch als Druck-Ausgabe, Paperback 978-0-12-370490-0 http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=193594 Aggregator Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Hennessy, John L. 1952- Computer architecture a quantitative approach Ordinateurs / Architecture Ordinateurs / Mémoires Parallélisme (Informatique) Systèmes enfouis (Informatique) / Conception et construction Réseaux d'ordinateurs Hiérarchie de mémoires (Informatique) Multiprocesseurs Arithmétique interne des ordinateurs COMPUTERS / Systems Architecture / General bisacsh Computer architecture fast Arquitetura e organização de computadores larpcal Architektur Computer architecture Konstruktion (DE-588)4032231-2 gnd Computerarchitektur (DE-588)4048717-9 gnd |
| subject_GND | (DE-588)4032231-2 (DE-588)4048717-9 |
| title | Computer architecture a quantitative approach |
| title_auth | Computer architecture a quantitative approach |
| title_exact_search | Computer architecture a quantitative approach |
| title_full | Computer architecture a quantitative approach John L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau [and others] |
| title_fullStr | Computer architecture a quantitative approach John L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau [and others] |
| title_full_unstemmed | Computer architecture a quantitative approach John L. Hennessy, David A. Patterson ; with contributions by Andrea C. Arpaci-Dusseau [and others] |
| title_short | Computer architecture |
| title_sort | computer architecture a quantitative approach |
| title_sub | a quantitative approach |
| topic | Ordinateurs / Architecture Ordinateurs / Mémoires Parallélisme (Informatique) Systèmes enfouis (Informatique) / Conception et construction Réseaux d'ordinateurs Hiérarchie de mémoires (Informatique) Multiprocesseurs Arithmétique interne des ordinateurs COMPUTERS / Systems Architecture / General bisacsh Computer architecture fast Arquitetura e organização de computadores larpcal Architektur Computer architecture Konstruktion (DE-588)4032231-2 gnd Computerarchitektur (DE-588)4048717-9 gnd |
| topic_facet | Ordinateurs / Architecture Ordinateurs / Mémoires Parallélisme (Informatique) Systèmes enfouis (Informatique) / Conception et construction Réseaux d'ordinateurs Hiérarchie de mémoires (Informatique) Multiprocesseurs Arithmétique interne des ordinateurs COMPUTERS / Systems Architecture / General Computer architecture Arquitetura e organização de computadores Architektur Konstruktion Computerarchitektur |
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