Design recipes for FPGAs: using verilog and VHDL
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Newnes
[2016]
|
| Ausgabe: | second edition |
| Schlagworte: | |
| Beschreibung: | xix, 369 Seiten Illustrationen |
| ISBN: | 9780080971292 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV043047773 | ||
| 003 | DE-604 | ||
| 005 | 20151127 | ||
| 007 | t | ||
| 008 | 151124s2016 a||| |||| 00||| eng d | ||
| 020 | |a 9780080971292 |c print |9 978-0-08-097129-2 | ||
| 035 | |a (OCoLC)936530128 | ||
| 035 | |a (DE-599)BVBBV043047773 | ||
| 040 | |a DE-604 |b ger |e rda | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-573 |a DE-29T | ||
| 084 | |a ST 170 |0 (DE-625)143602: |2 rvk | ||
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 100 | 1 | |a Wilson, Peter R. |e Verfasser |0 (DE-588)139125167 |4 aut | |
| 245 | 1 | 0 | |a Design recipes for FPGAs |b using verilog and VHDL |c Peter Wilson |
| 250 | |a second edition | ||
| 264 | 1 | |a Amsterdam |b Newnes |c [2016] | |
| 264 | 4 | |c ©2016 | |
| 300 | |a xix, 369 Seiten |b Illustrationen | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Field programmable gate array |0 (DE-588)4347749-5 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Field programmable gate array |0 (DE-588)4347749-5 |D s |
| 689 | 0 | 1 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | 2 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | |5 DE-604 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-028472236 | ||
Datensatz im Suchindex
| _version_ | 1804175415551459328 |
|---|---|
| any_adam_object | |
| author | Wilson, Peter R. |
| author_GND | (DE-588)139125167 |
| author_facet | Wilson, Peter R. |
| author_role | aut |
| author_sort | Wilson, Peter R. |
| author_variant | p r w pr prw |
| building | Verbundindex |
| bvnumber | BV043047773 |
| classification_rvk | ST 170 ST 250 |
| ctrlnum | (OCoLC)936530128 (DE-599)BVBBV043047773 |
| discipline | Informatik |
| edition | second edition |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01275nam a2200385 c 4500</leader><controlfield tag="001">BV043047773</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20151127 </controlfield><controlfield tag="007">t</controlfield><controlfield tag="008">151124s2016 a||| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780080971292</subfield><subfield code="c">print</subfield><subfield code="9">978-0-08-097129-2</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)936530128</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV043047773</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rda</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-573</subfield><subfield code="a">DE-29T</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 170</subfield><subfield code="0">(DE-625)143602:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Wilson, Peter R.</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)139125167</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Design recipes for FPGAs</subfield><subfield code="b">using verilog and VHDL</subfield><subfield code="c">Peter Wilson</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">second edition</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Amsterdam</subfield><subfield code="b">Newnes</subfield><subfield code="c">[2016]</subfield></datafield><datafield tag="264" ind1=" " ind2="4"><subfield code="c">©2016</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">xix, 369 Seiten</subfield><subfield code="b">Illustrationen</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Field programmable gate array</subfield><subfield code="0">(DE-588)4347749-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="2"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-028472236</subfield></datafield></record></collection> |
| id | DE-604.BV043047773 |
| illustrated | Illustrated |
| indexdate | 2024-07-10T07:15:56Z |
| institution | BVB |
| isbn | 9780080971292 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-028472236 |
| oclc_num | 936530128 |
| open_access_boolean | |
| owner | DE-573 DE-29T |
| owner_facet | DE-573 DE-29T |
| physical | xix, 369 Seiten Illustrationen |
| publishDate | 2016 |
| publishDateSearch | 2016 |
| publishDateSort | 2016 |
| publisher | Newnes |
| record_format | marc |
| spelling | Wilson, Peter R. Verfasser (DE-588)139125167 aut Design recipes for FPGAs using verilog and VHDL Peter Wilson second edition Amsterdam Newnes [2016] ©2016 xix, 369 Seiten Illustrationen txt rdacontent n rdamedia nc rdacarrier VHDL (DE-588)4254792-1 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 s VERILOG (DE-588)4268385-3 s VHDL (DE-588)4254792-1 s DE-604 |
| spellingShingle | Wilson, Peter R. Design recipes for FPGAs using verilog and VHDL VHDL (DE-588)4254792-1 gnd VERILOG (DE-588)4268385-3 gnd Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4254792-1 (DE-588)4268385-3 (DE-588)4347749-5 |
| title | Design recipes for FPGAs using verilog and VHDL |
| title_auth | Design recipes for FPGAs using verilog and VHDL |
| title_exact_search | Design recipes for FPGAs using verilog and VHDL |
| title_full | Design recipes for FPGAs using verilog and VHDL Peter Wilson |
| title_fullStr | Design recipes for FPGAs using verilog and VHDL Peter Wilson |
| title_full_unstemmed | Design recipes for FPGAs using verilog and VHDL Peter Wilson |
| title_short | Design recipes for FPGAs |
| title_sort | design recipes for fpgas using verilog and vhdl |
| title_sub | using verilog and VHDL |
| topic | VHDL (DE-588)4254792-1 gnd VERILOG (DE-588)4268385-3 gnd Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | VHDL VERILOG Field programmable gate array |
| work_keys_str_mv | AT wilsonpeterr designrecipesforfpgasusingverilogandvhdl |