VLSI test principles and architectures: design for testability
Gespeichert in:
| Format: | Elektronisch E-Book |
|---|---|
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Elsevier Morgan Kaufmann Publishers
©2006
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Online-Zugang: | FAW01 FAW02 Volltext |
| Beschreibung: | Includes bibliographical references and index Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website |
| Beschreibung: | 1 Online-Ressource (xxx, 777 pages) |
| ISBN: | 0080474799 9780080474793 |
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| id | DE-604.BV043044400 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:15:50Z |
| institution | BVB |
| isbn | 0080474799 9780080474793 |
| language | English |
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| spelling | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen Amsterdam Elsevier Morgan Kaufmann Publishers ©2006 1 Online-Ressource (xxx, 777 pages) txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes bibliographical references and index Design for testability / Laung-Terng (L.-T.) Wang, Xiaoqing Wen, and Khader S. Abdel-Hafez -- Logic and fault simulation / Jiun-Lang Huang, James C.-M. Li, and Duncan M. (Hank) Walker -- Test generation / Michael S. Hsiao -- Logic built-in self-test / Laung-Terng (L.-T.) Wang -- Test compression / Xiaowei Li, Kuen-Jong Lee, and Nur A. Touba -- Logic diagnosis / Shi-Yu Huang -- Memory testing and built-in self-test / Cheng-Wen Wu -- Memory diagnosis and built-in self-repair / Cheng-Wen Wu -- Boundary scan and core-based testing / Kuen-Jong Lee -- Analog and mixed-signal testing / Chauchin Su -- Test technology trends in the nanometer age / Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website Circuits intégrés à très grande échelle / Essais Circuits intégrés à très grande échelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Circuitos integrados vlsi larpcal Testen swd VLSI. swd Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf VLSI (DE-588)4117388-0 s Testen (DE-588)4367264-4 s 1\p DE-604 Wang, Laung-Terng Sonstige oth Wu, Cheng-Wen Sonstige oth Wen, Xiaoqing Sonstige oth Erscheint auch als Druck-Ausgabe, Hardcover 0-12-370597-5 Erscheint auch als Druck-Ausgabe, Hardcover 978-0-12-370597-6 http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=189477 Aggregator Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | VLSI test principles and architectures design for testability Circuits intégrés à très grande échelle / Essais Circuits intégrés à très grande échelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Circuitos integrados vlsi larpcal Testen swd VLSI. swd Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4367264-4 (DE-588)4117388-0 |
| title | VLSI test principles and architectures design for testability |
| title_auth | VLSI test principles and architectures design for testability |
| title_exact_search | VLSI test principles and architectures design for testability |
| title_full | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_fullStr | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_full_unstemmed | VLSI test principles and architectures design for testability edited by Laung-Terng Wang, Cheng-Wen Wu, Xiaoqing Wen |
| title_short | VLSI test principles and architectures |
| title_sort | vlsi test principles and architectures design for testability |
| title_sub | design for testability |
| topic | Circuits intégrés à très grande échelle / Essais Circuits intégrés à très grande échelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. bisacsh TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic bisacsh COMPUTERS / Logic Design bisacsh Integrated circuits / Very large scale integration / Testing blmlsh Integrated circuits / Very large scale integration / Design blmlsh Integrated circuits / Very large scale integration / Design fast Integrated circuits / Very large scale integration / Testing fast Circuitos integrados vlsi larpcal Testen swd VLSI. swd Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design Testen (DE-588)4367264-4 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Circuits intégrés à très grande échelle / Essais Circuits intégrés à très grande échelle / Conception et construction TECHNOLOGY & ENGINEERING / Electronics / Circuits / VLSI & ULSI. TECHNOLOGY & ENGINEERING / Electronics / Circuits / Logic COMPUTERS / Logic Design Integrated circuits / Very large scale integration / Testing Integrated circuits / Very large scale integration / Design Circuitos integrados vlsi Testen VLSI. Integrated circuits Very large scale integration Testing Integrated circuits Very large scale integration Design VLSI |
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