On application-specific network-on-chip synthesis and on-chip trace and debug:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
München
Verlag Dr. Hut
2015
|
| Ausgabe: | 1. Auflage |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | ix, 171 Seiten Illustrationen, Diagramme |
| ISBN: | 9783843923026 |
Internformat
MARC
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| 100 | 1 | |a Todorov, Vladimir |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a On application-specific network-on-chip synthesis and on-chip trace and debug |c Vladimir Todorov |
| 250 | |a 1. Auflage | ||
| 264 | 1 | |a München |b Verlag Dr. Hut |c 2015 | |
| 300 | |a ix, 171 Seiten |b Illustrationen, Diagramme | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
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| 502 | |b Dissertation |c Technische Universität München |d 2015 | ||
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Datensatz im Suchindex
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| adam_text | CONTENTS
1. INTRODUCTION 1
1.1. SYSTEM-ON-CHIP DESIGN FLOW 3
1.2. MOTIVATION 5
1.3. STATE-OF-THE-ART 6
1.3.1. APPLICATION-SPECIFIC NETWORK-ON-CHIP SYNTHESIS 6
1.3.2. ON-CHIP TRACE & DEBUG 7
1.4. CONTRIBUTIONS OF THIS WORK 8
1.4.1. APPLICATION-SPECIFIC NETWORK-ON-CHIP SYNTHESIS 8
1.4.2. ON-CHIP TRACE & DEBUG 10
1.5. PREVIOUS PUBLICATIONS 12
1.6. STRUCTURE OF THIS WORK 12
2. NETWORKS-ON-CHIP 15
2.1. NETWORK-ON-CHIP PACKET 15
2.2. NETWORK-ON-CHIP BUILDING BLOCKS 16
2.2.1. NETWORK INTERFACE 16
2.2.2. NETWORK-ON-CHIP ROUTER 17
2.2.3. VIRTUAL CHANNELS 17
2.3. NETWORK-ON-CHIP TOPOLOGIES 19
2.3.1. DESIGNING NETWORK-ON-CHIP TOPOLOGIES 19
2.4. ROUTING IN NETWORKS-ON-CHIP 20
2.4.1. PACKET SWITCHING 21
2.4.2. FLOW CONTROL 21
2.4.3. PACKET ROUTING ALGORITHM 22
2.4.4. DEADLOCK 22
2.5. SUMMARY 23
3. APPLICATION-SPECIFIC NETWORK-ON-CHIP SYNTHESIS 25
3.1. NETWORK-ON-CHIP SYNTHESIS FLOW 25
3.1.1. SYSTEM-ON-CHIP SPECIFICATION 25
3.1.2. PROPOSED SYNTHESIS FLOW 27
3.2. PARTITIONING & ROUTER INSERTION 30
3.2.1. USE CASE PARTITIONING 30
3.2.2. FLOORPLAN PARTITIONING 36
3.2.3. DOMAIN PARTITIONING 37
3.2.4. SYSTEM PARTITIONING AND ROUTER INSTANTIATION 38
3.2.5. ROUTER INSTANTIATION 42
VII
HTTP://D-NB.INFO/1078741980
CONTENTS
3.2.6. ROUTER SPLITTING 43
3.3. HYBRIDIZATION 48
3.4. RELAY ROUTER INSERTION 51
3.5. FLOW ROUTING & LINK INSERTION 54
3.5.1. PROCESSING OF COMMUNICATION FLOWS 55
3.5.2. CHANNEL ROUTING GRAPH 56
3.5.3. COST & DELAY OF ROUTING STEPS 57
3.5.4. DELAY-BOUNDED BINARY SEARCH 59
3.5.5. A* SEARCH WITH CONSTRAINTS 61
3.5.6. DEADLOCK DETECTION & AVOIDANCE 65
3.5.7. PACKET ROUTING ALGORITHM 69
3.5.8. FLOW ROUTING IN A HYBRID NOC 70
3.5.9. RESTARTING ON FAILURE 71
3.5.10. PRODUCER-CONSUMER MODEL 72
3.6. SUMMARY 74
4. EXPERIMENTAL RESULTS: APPLICATION-SPECIFIC NETWORK-ON-CHIP SYNTHESIS
75
4.1. EXPERIMENTAL SETUP 75
4.1.1. SOC EXAMPLE SPECIFICATIONS 75
4.1.2. NETWORK-ON-CHIP (NOC) SIMULATION 76
4.2. SOC PARTITIONING * 76
4.2.1. AREA RESULTS 76
4.2.2. LATENCY RESULTS 77
4.3. FLOW ROUTING 80
4.3.1. AREA RESULTS 80
4.3.2. LATENCY RESULTS 80
4.4. HYBRID NOC SYNTHESIS 84
4.4.1. AREA RESULTS 84
4.4.2. LATENCY RESULTS 84
4.4.3. TOPOLOGY CHARACTERISTICS 85
4.5. FLOW ROUTING ALGORITHMS, RELAY ROUTERS, AND VIRTUAL CHANNELS 88
4.5.1. NOC RESULTS FOR SOCL 88
4.5.2. NOC RESULTS FOR SOC2 90
4.5.3. HYBRID NOC (HNOC) RESULTS FOR SOCL 91
4.5.4. HNOC RESULTS FOR SOC2 91
4.6. PRODUCER-CONSUMER MODEL 93
4.7. EXECUTION TIME 94
4.8. EXAMPLE TOPOLOGIES 95
4.9. SUMMARY 95
5. TRACE & DEBUG NETWORK-ON-CHIP 99
5.1. SYSTEM TRACE 99
5.2. TDNOC MONITORS 100
5.3. COMMUNICATION ARCHITECTURE 101
5.3.1. HIERARCHICAL RING STRUCTURE 102
5.3.2. MULTILEVEL HIERARCHICAL RING 108
VIII
CONTENTS
5.4. DIFFERENTIAL TIMESTAMPING 112
5.4.1. TIMESTAMPING IN GALS SOCS 112
5.4.2. TIMESTAMPING IN DVFS SOCS 118
5.5. SUMMARY 123
6. EXPERIMENTAL RESULTS - TEST AND DEBUG NETWORK-ON-CHIP 125
6.1. TDNOC SETUP 125
6.2. TDNOC PERFORMANCE AND COST 126
6.2.1. PERFORMANCE 126
6.2.2. COST 130
6.3. ARBITRATION FAIRNESS 130
6.4. TIMESTAMPING 131
6.4.1. PARTIAL POWER DOWN 131
6.4.2. FREQUENCY SWITCHING 132
6.5. SUMMARY 133
7. CONCLUSION 135
7.1. APPLICATION-SPECIFIC NETWORK-ON-CHIP SYNTHESIS 136
7.2. TRACE & DEBUG NETWORK-ON-CHIP 138
A. ON PARTITIONING . 141
A.L. LAPLACIAN MATRIX 141
A.2. NORMALIZED MUTUAL INFORMATION 142
B. VARIANCE REDUCTION 145
BIBLIOGRAPHY 149
LIST OF FIGURES 159
LIST OF TABLES 163
ACRONYMS 165
GLOSSARY 167
IX
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| bvnumber | BV043008955 |
| classification_tum | ELT 272d |
| ctrlnum | (OCoLC)934889922 (DE-599)BVBBV043008955 |
| discipline | Elektrotechnik |
| edition | 1. Auflage |
| format | Thesis Book |
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| isbn | 9783843923026 |
| language | English |
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| spelling | Todorov, Vladimir Verfasser aut On application-specific network-on-chip synthesis and on-chip trace and debug Vladimir Todorov 1. Auflage München Verlag Dr. Hut 2015 ix, 171 Seiten Illustrationen, Diagramme txt rdacontent n rdamedia nc rdacarrier Dissertation Technische Universität München 2015 Debugging (DE-588)4148954-8 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf Network-on-Chip (DE-588)1079563938 gnd rswk-swf Zeitstempel (DE-588)4629528-8 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Programmlaufzeit (DE-588)4745613-9 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Ablaufverfolgung (DE-588)4767115-4 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content System-on-Chip (DE-588)4740357-3 s Network-on-Chip (DE-588)1079563938 s Debugging (DE-588)4148954-8 s Ablaufverfolgung (DE-588)4767115-4 s Zeitstempel (DE-588)4629528-8 s Programmlaufzeit (DE-588)4745613-9 s Entwurfsautomation (DE-588)4312536-0 s Kundenspezifische Schaltung (DE-588)4122250-7 s DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=028433947&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Todorov, Vladimir On application-specific network-on-chip synthesis and on-chip trace and debug Debugging (DE-588)4148954-8 gnd System-on-Chip (DE-588)4740357-3 gnd Network-on-Chip (DE-588)1079563938 gnd Zeitstempel (DE-588)4629528-8 gnd Entwurfsautomation (DE-588)4312536-0 gnd Programmlaufzeit (DE-588)4745613-9 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Ablaufverfolgung (DE-588)4767115-4 gnd |
| subject_GND | (DE-588)4148954-8 (DE-588)4740357-3 (DE-588)1079563938 (DE-588)4629528-8 (DE-588)4312536-0 (DE-588)4745613-9 (DE-588)4122250-7 (DE-588)4767115-4 (DE-588)4113937-9 |
| title | On application-specific network-on-chip synthesis and on-chip trace and debug |
| title_auth | On application-specific network-on-chip synthesis and on-chip trace and debug |
| title_exact_search | On application-specific network-on-chip synthesis and on-chip trace and debug |
| title_full | On application-specific network-on-chip synthesis and on-chip trace and debug Vladimir Todorov |
| title_fullStr | On application-specific network-on-chip synthesis and on-chip trace and debug Vladimir Todorov |
| title_full_unstemmed | On application-specific network-on-chip synthesis and on-chip trace and debug Vladimir Todorov |
| title_short | On application-specific network-on-chip synthesis and on-chip trace and debug |
| title_sort | on application specific network on chip synthesis and on chip trace and debug |
| topic | Debugging (DE-588)4148954-8 gnd System-on-Chip (DE-588)4740357-3 gnd Network-on-Chip (DE-588)1079563938 gnd Zeitstempel (DE-588)4629528-8 gnd Entwurfsautomation (DE-588)4312536-0 gnd Programmlaufzeit (DE-588)4745613-9 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Ablaufverfolgung (DE-588)4767115-4 gnd |
| topic_facet | Debugging System-on-Chip Network-on-Chip Zeitstempel Entwurfsautomation Programmlaufzeit Kundenspezifische Schaltung Ablaufverfolgung Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=028433947&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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