Computer architecture: a quantitative approach
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| Main Authors: | , |
|---|---|
| Format: | Book |
| Language: | English |
| Published: |
Cambridge, MA
Morgan Kaufmann Publishers
[2019]
|
| Edition: | Sixth edition |
| Subjects: | |
| Online Access: | Inhaltsverzeichnis Klappentext |
| Physical Description: | xxix, 617 Seiten, A-55, B-67, C-78, R-36, I-48 Illustrationen, Diagramme |
| ISBN: | 9780128119051 |
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| adam_text | Contents Foreword Chapter Ί ix Preface xvii Acknowledgments xxv Fundamentals of Quantitative Design and Analysis 1.1 .1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 Introduction Classes of Computers Defining Computer Architecture Trends in Technology Trends in Power and Energy in integrated Circuits Trends in Cost Dependability Measuring, Reporting, and Summarizing Performance Quantitative Principles of Computer Design Putting It All Together: Performance, Price, and Power Fallacies and Pitfalls Concluding Remarks Historical Perspectives and References Case Studies and Exercises by Diana Franklin • Chapter 2 2 б 11 18 23 29 36 39 48 55 58 64 67 67 * Memory Hierarchy Design 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Introduction Memory Technology and Optimizations Ten Advanced Optimizations of Cache Performance Virtual Memory and Virtual Machines Cross-Cutting issues: The Design of Memory Hierarchies Putting It All Together: Memory Hierarchies in the ARM Cortex-A53 and Intel Core І7 6700 Fallacies and Pitfalls Concluding Remarks: Looking Ahead Historical Perspectives and References 78 84 94 118 126 129 142 146 148 xi
xii н Contents Case Studies and Exercises by Norman P. Jouppi, Rajeev Balasubramonian, Naveen Muralimanohar, and Sheng Li Chapter 3 Instruction-Level Parallelism and Its Exploitation 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 Chapter 4 Instruction-Level Parallelism: Concepts and Challenges Basic Compiler Techniques for Exposing ILP Reducing Branch Costs With Advanced Branch Prediction Overcoming Data Hazards With Dynamic Scheduling Dynamic Scheduling: Examples and the Algorithm Hardware-Based Speculation Exploiting ILP Using Multiple issue and Static Scheduling Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation Advanced Techniques for Instruction Delivery and Speculation Cross-Cutting Issues Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput Putting It All Together: The Intel Core ¡7 6700 and ARM Cortex-A53 Fallacies and Pitfalls Concluding Remarks: What s Ahead? Historical Perspective and References Case Studies and Exercises by Jason D. Bakos and Robert P. Colwell 168 176 182 191 201 208 218 222 228 240 242 247 258 264 266 266 Data-Level Parallelism in Vector, SIMD, and GPU Architectures 4.1 Introduction 4.2 Vector Architecture 4.3 SIMD Instruction Set Extensions for Multimedia 4.4 Graphics Processing Units 4.5 Detecting and Enhancing Loop-Level Parallelism 4.6 Cross-Cutting Issues 4.7 Putting It All Together: Embedded Versus Server GPUs and Tesla Versus Core І7 4.8 Fallacies and Pitfalls 4.9 Concluding Remarks 4.10 Historical Perspective and References Case Study and Exercises by Jason D.
Bakos Chapter 5 148 282 283 304 310 336 345 346 353 357 357 357 Thread-Level Parallelism 5.1 5.2 5.3 Introduction Centralized Shared-Memory Architectures Performance of Symmetric Shared-Memory Multiprocessors 368 377 393
Contents 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 Chapter б Distributed Shared-Memory and Directory-Based Coherence Synchronization: The Basics Models of Memory Consistency: An Introduction Cross-Cutting Issues Putting It All Together: Multicore Processors and Their Performance. Fallacies and Pitfalls The Future of Multicore Scaling Concluding Remarks Historical Perspectives and References Case Studies and Exercises by Amr Zaky and David A. Wood · ХІІІ 404 412 417 422 426 438 442 444 445 446 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism 6.1 6.2 Introduction Programming Models and Workloads for Warehouse-Scale Computers 6.3 Computer Architecture of Warehouse-Scale Computers 6.4 The Efficiency and Cost of Warehouse-Scale Computers 6.5 Cloud Computing: The Return of Utility Computing 6.6 Cross-Cutting Issues 6.7 Putting It All Together: A Google Warehouse-Scale Computer 6.8 Fallacies and Pitfalls _ 6.9 Concluding Remarks 6.10 Historical Perspectives and References Case Studies and Exercises by Parthasarathy Ranganathan Chapter 7 и 466 471 477 482 490 501 503 514 518 519 519 Domain-Specific Architectures 7.1 7.2 7.3 7.4 Introduction Guidelines for DSAs Example Domain: Deep Neural Networks Google s Tensor Processing Unit, an Inference Data Center Accelerator 7.5 Microsoft Catapult, a Flexible Data Center Accelerator 7.6 Intel Crest, a Data Center Accelerator for Training 7.7 Pixel Visual Core, a Personal Mobile Device Image Processing Unit 7.8 Cross-Cutting Issues 7.9 Putting It All Together: CPUs Versus GPUs Versus DNN Accelerators 7.10 Fallacies
and Pitfalls 7.11 Concluding Remarks 7.12 Historical Perspectives and References Case Studies and Exercises by Cliff Young 540 543 544 557 567 579 579 592 595 602 604 606 606
xiv и Contents Appendix A Instruction Set Principles A.1 A.2 A3 A.4 A.5 A.6 A.7 A.8 A.9 A.10 A.11 A.12 Appendix В A-2 A-3 A-7 A-13 A-15 A-16 A-21 A-24 A-33 A-42 A-46 A-47 A-47 Review of Memory Hierarchy B.1 B.2 B.3 B.4 B.5 B.6 B.7 B.8 Appendix C Introduction Classifying Instruction Set Architectures Memory Addressing Type and Size of Operands Operations In the Instruction Set Instructions for Control Flow Encoding an Instruction Set Cross-Cutting Issues: The Role of Compilers Putting It All Together: The RISC-V Architecture Fallacies and Pitfalls Concluding Remarks Historical Perspective and References Exercises by Gregory D. Peterson Introduction . Cache Performance Six Basic Cache Optimizations Virtual Memory Protection and Examples of Virtual Memory Fallacies and Pitfalls Concluding Remarks Historical Perspective and References Exercises by Amr Zaky B-2 B-15 B-22 B-40 B-49 B-57 B-59 B-59 B-60 Pipelining: Basic and Intermediate Concepts C.1 C.2 C.3 C.4 C.5 Introduction The Major Hurdle of Pipelining—PipelineHazards How Is Pipelining Implemented? What Makes Pipelining Hard to Implement? Extending the RISC V Integer Pipeline to Handle Multicycle Operations C.6 Putting It All Together: The MIPS R4000Pipeline C.7 Cross-Cutting Issues C.8 Fallacies and Pitfalls C.9 Concluding Remarks 1 C.10 Historical Perspective and References Updated Exercises by Diana Franklin C-2 C-10 C-26 C-37 C-45 C-55 C-65 C-70 C-71 C-71 C-71
Contents a XV Online Appendices Appendix D Storage Systems Appendix E Embedded Systems by Thomas M. Conte Appendix F Interconnection Networks by Timothy M. Pinkston and José Duato Appendix G Vector Processors in More Depth by Krste Asanovic Appendix H Hardware and Software for VLIW and EPIC Appendix I Large-Scale Multiprocessors and Scientific Applications Appendix J Computer Arithmetic by David Goldberg Appendix К Survey of Instruction Set Architectures Appendix L Advanced Concepts on Address Translation by Abhishek Bhattacharjee Appendix M Historical Perspectives and References References Index R-1 И
COMPUTER ARCHITECTURE Sixth Edition A Quantitative Approach John L. Hennessy I David A. Patterson Foreword by Norman P. Jouppi “This sixth edition comes at a critical time: Moore’s Law is fading just as deep learning demands unprecedented compute cycles. The new chapter on domain-specific architectures documents a number of promising approaches and prophesies a rebirth in computer architecture. Like the scholars of the European Renaissance, computer architects must understand our own history, and then combine the lessons of that history with new techniques to remake the world.” —Cliff Young, Google Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students, and practitioners of computer design for nearly 30 years. The sixth edition of this classic textbook is fully revised with the latest developments In processor and system architecture. It now features examples from the RISC-V (“RISC Five”) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also Includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google’s newest WSC. True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design. Features ■ Includes a new chapter on domain-specific
architectures, explaining how they are the only path forward for improved performance and energy efficiency given the end of Moore’s Law and Dennard scaling ■ Features the introduction of four DSAs from industry: Google Tensor Processing Unit, Google Pixel Visual Core, Intel Nervana Neural Network Processor, and Microsoft Catapult ■ Features extensive updates to the chapter on warehouse-scale computing, with the first public information on the newest Google WSC ■ Offers updates to other chapters Including new material dealing with the use of stacked DRAM; data on the performance of new NVIDIA Pascal GPU vs. new AVX-512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organization
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| title | Computer architecture a quantitative approach |
| title_auth | Computer architecture a quantitative approach |
| title_exact_search | Computer architecture a quantitative approach |
| title_full | Computer architecture a quantitative approach John L. Hennessy, Stanford University, David A. Patterson, University of California, Berkeley |
| title_fullStr | Computer architecture a quantitative approach John L. Hennessy, Stanford University, David A. Patterson, University of California, Berkeley |
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| title_short | Computer architecture |
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Indexes
THWS Würzburg Zentralbibliothek Lesesaal
| Call Number: |
1000 ST 150 H515(6) |
|---|---|
| Copy 1 | ausleihbar Available Place a Hold |