Plasma etching processes for interconnect realization in VLSI:
This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions
Gespeichert in:
| Weitere Verfasser: | |
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| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
London
ISTE Press
2015
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| Schlagworte: | |
| Online-Zugang: | Volltext |
| Zusammenfassung: | This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions |
| Beschreibung: | Includes bibliographical references and index Front Cover ; Plasma Etching Processes for Interconnect Realization in VLSI; Copyright ; Contents ; List of Acronyms ; Preface ; Chapter 1: Introduction ; 1.1. Integration Processes Related to Copper Introduction ; 1.2. Dielectric Material with Low-k Value (<4) ; Chapter 2: Interaction Plasma/Dielectric; 2.1. Porous SiOCH Film Etching; 2.2. Porous SiOCH Film Sensitivity to Post-Etch Treatments ; Chapter 3: Porous SiOCH Film Integration; 3.1. Trench First Metallic Hard Mask Integration ; 3.2. Porous SiOCH Integration Using the Via First Approach ; 3.3. Summary Chapter 4: Interconnects for Tomorrow 4.1. Consequence of Porosity Increase ; 4.2. Process Solutions for Dielectric Constant Reduction ; 4.3. Material Solutions for Dielectric Constant Reduction ; 4.4. Alternative Interconnect Architectures for Dielectric Constant Reduction ; 4.5. Conclusion ; Bibliography ; List of Authors ; Index |
| Beschreibung: | 1 online resource |
| ISBN: | 9780081005903 0081005903 |
Internformat
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| 245 | 1 | 0 | |a Plasma etching processes for interconnect realization in VLSI |c edited by Nicolas Posseme |
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| 500 | |a Includes bibliographical references and index | ||
| 500 | |a Front Cover ; Plasma Etching Processes for Interconnect Realization in VLSI; Copyright ; Contents ; List of Acronyms ; Preface ; Chapter 1: Introduction ; 1.1. Integration Processes Related to Copper Introduction ; 1.2. Dielectric Material with Low-k Value (<4) ; Chapter 2: Interaction Plasma/Dielectric; 2.1. Porous SiOCH Film Etching; 2.2. Porous SiOCH Film Sensitivity to Post-Etch Treatments ; Chapter 3: Porous SiOCH Film Integration; 3.1. Trench First Metallic Hard Mask Integration ; 3.2. Porous SiOCH Integration Using the Via First Approach ; 3.3. Summary | ||
| 500 | |a Chapter 4: Interconnects for Tomorrow 4.1. Consequence of Porosity Increase ; 4.2. Process Solutions for Dielectric Constant Reduction ; 4.3. Material Solutions for Dielectric Constant Reduction ; 4.4. Alternative Interconnect Architectures for Dielectric Constant Reduction ; 4.5. Conclusion ; Bibliography ; List of Authors ; Index | ||
| 520 | |a This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions | ||
| 650 | 7 | |a TECHNOLOGY & ENGINEERING / Mechanical |2 bisacsh | |
| 650 | 7 | |a Integrated circuits / Very large scale integration |2 fast | |
| 650 | 7 | |a Molded interconnect devices |2 fast | |
| 650 | 7 | |a Plasma etching |2 fast | |
| 650 | 4 | |a Integrated circuits / Very large scale integration | |
| 650 | 4 | |a Plasma etching | |
| 650 | 4 | |a Molded interconnect devices | |
| 700 | 1 | |a Posseme, Nicolas |4 edt | |
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| illustrated | Not Illustrated |
| indexdate | 2024-07-10T07:13:19Z |
| institution | BVB |
| isbn | 9780081005903 0081005903 |
| language | English |
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| spelling | Plasma etching processes for interconnect realization in VLSI edited by Nicolas Posseme London ISTE Press 2015 1 online resource txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references and index Front Cover ; Plasma Etching Processes for Interconnect Realization in VLSI; Copyright ; Contents ; List of Acronyms ; Preface ; Chapter 1: Introduction ; 1.1. Integration Processes Related to Copper Introduction ; 1.2. Dielectric Material with Low-k Value (<4) ; Chapter 2: Interaction Plasma/Dielectric; 2.1. Porous SiOCH Film Etching; 2.2. Porous SiOCH Film Sensitivity to Post-Etch Treatments ; Chapter 3: Porous SiOCH Film Integration; 3.1. Trench First Metallic Hard Mask Integration ; 3.2. Porous SiOCH Integration Using the Via First Approach ; 3.3. Summary Chapter 4: Interconnects for Tomorrow 4.1. Consequence of Porosity Increase ; 4.2. Process Solutions for Dielectric Constant Reduction ; 4.3. Material Solutions for Dielectric Constant Reduction ; 4.4. Alternative Interconnect Architectures for Dielectric Constant Reduction ; 4.5. Conclusion ; Bibliography ; List of Authors ; Index This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions TECHNOLOGY & ENGINEERING / Mechanical bisacsh Integrated circuits / Very large scale integration fast Molded interconnect devices fast Plasma etching fast Integrated circuits / Very large scale integration Plasma etching Molded interconnect devices Posseme, Nicolas edt http://www.sciencedirect.com/science/book/9781785480157 Verlag Volltext |
| spellingShingle | Plasma etching processes for interconnect realization in VLSI TECHNOLOGY & ENGINEERING / Mechanical bisacsh Integrated circuits / Very large scale integration fast Molded interconnect devices fast Plasma etching fast Integrated circuits / Very large scale integration Plasma etching Molded interconnect devices |
| title | Plasma etching processes for interconnect realization in VLSI |
| title_auth | Plasma etching processes for interconnect realization in VLSI |
| title_exact_search | Plasma etching processes for interconnect realization in VLSI |
| title_full | Plasma etching processes for interconnect realization in VLSI edited by Nicolas Posseme |
| title_fullStr | Plasma etching processes for interconnect realization in VLSI edited by Nicolas Posseme |
| title_full_unstemmed | Plasma etching processes for interconnect realization in VLSI edited by Nicolas Posseme |
| title_short | Plasma etching processes for interconnect realization in VLSI |
| title_sort | plasma etching processes for interconnect realization in vlsi |
| topic | TECHNOLOGY & ENGINEERING / Mechanical bisacsh Integrated circuits / Very large scale integration fast Molded interconnect devices fast Plasma etching fast Integrated circuits / Very large scale integration Plasma etching Molded interconnect devices |
| topic_facet | TECHNOLOGY & ENGINEERING / Mechanical Integrated circuits / Very large scale integration Molded interconnect devices Plasma etching |
| url | http://www.sciencedirect.com/science/book/9781785480157 |
| work_keys_str_mv | AT possemenicolas plasmaetchingprocessesforinterconnectrealizationinvlsi |