Low power interconnect design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
New York, NY [u.a.]
Springer
2015
|
| Schlagworte: | |
| Online-Zugang: | BHS01 BTU01 FAB01 FAW01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext Inhaltsverzeichnis Abstract |
| Beschreibung: | 1 Online-Ressource (XVII, 152 p. 111 illus., 12 illus. in color) |
| ISBN: | 9781461413233 |
| DOI: | 10.1007/978-1-4614-1323-3 |
Internformat
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Datensatz im Suchindex
| DE-BY-FWS_katkey | 568401 |
|---|---|
| _version_ | 1806179309623181312 |
| adam_text | LOW POWER INTERCONNECT DESIGN
/ SAINI, SANDEEP
: 2015
TABLE OF CONTENTS / INHALTSVERZEICHNIS
PART I BASICS OF INTERCONNECT DESIGN
INTRODUCTION TO INTERCONNECTS
CMOS BUFFER
PART II BUFFER AND SCHMIDT TRIGGER INSERTION TECHNIQUES FOR LOW POWER
INTERCONNECT DESIGN
BUFFER INSERTION AS A SOLUTION TO INTERCONNECT ISSUES
SCHMIDT TRIGGER APPROACH
PART III BUS CODING TECHNIQUES FOR LOW POWER INTERCONNECT DESIGN
BUS CODING TECHNIQUES
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
LOW POWER INTERCONNECT DESIGN
/ SAINI, SANDEEP
: 2015
ABSTRACT / INHALTSTEXT
THIS BOOK PROVIDES PRACTICAL SOLUTIONS FOR DELAY AND POWER REDUCTION FOR
ON-CHIP INTERCONNECTS AND BUSES. IT PROVIDES AN IN DEPTH DESCRIPTION
OF THE PROBLEM OF SIGNAL DELAY AND EXTRA POWER CONSUMPTION, POSSIBLE
SOLUTIONS FOR DELAY AND GLITCH REMOVAL, WHILE CONSIDERING THE POWER
REDUCTION OF THE TOTAL SYSTEM. COVERAGE FOCUSES ON USE OF THE SCHMITT
TRIGGER AS AN ALTERNATIVE APPROACH TO BUFFER INSERTION FOR DELAY AND
POWER REDUCTION IN VLSI INTERCONNECTS. IN THE LAST SECTION OF THE BOOK,
VARIOUS BUS CODING TECHNIQUES ARE DISCUSSED TO MINIMIZE DELAY AND POWER
IN ADDRESS AND DATA BUSES. PROVIDES PRACTICAL
SOLUTIONS FOR DELAY AND POWER REDUCTION FOR ON-CHIP INTERCONNECTS AND
BUSES; FOCUSES ON DEEP SUB MICRON TECHNOLOGY DEVICES
AND INTERCONNECTS; OFFERS IN DEPTH ANALYSIS OF DELAY,
INCLUDING DETAILS REGARDING CROSSTALK AND PARASITICS;
DESCRIBES USE OF THE SCHMITT TRIGGER AS A VERSATILE
ALTERNATIVE APPROACH TO BUFFER INSERTION FOR DELAY AND POWER REDUCTION
IN VLSI INTERCONNECTS; PROVIDES DETAILED SIMULATION
RESULTS TO SUPPORT THE THEORETICAL DISCUSSIONS.
PROVIDES DETAILS OF DELAY AND POWER EFFICIENT BUS CODING TECHNIQUES
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
|
| any_adam_object | 1 |
| author | Saini, Sandeep |
| author_facet | Saini, Sandeep |
| author_role | aut |
| author_sort | Saini, Sandeep |
| author_variant | s s ss |
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| bvnumber | BV042669280 |
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| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4614-1323-3 |
| format | Electronic eBook |
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| id | DE-604.BV042669280 |
| illustrated | Not Illustrated |
| indexdate | 2024-08-01T12:06:57Z |
| institution | BVB |
| isbn | 9781461413233 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-028101364 |
| oclc_num | 915352070 |
| open_access_boolean | |
| owner | DE-1046 DE-1043 DE-B768 DE-Aug4 DE-898 DE-BY-UBR DE-573 DE-859 DE-863 DE-BY-FWS DE-634 DE-92 DE-862 DE-BY-FWS DE-861 DE-706 |
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| spellingShingle | Saini, Sandeep Low power interconnect design Engineering Computer science Electronics Systems engineering Circuits and Systems Electronics and Microelectronics, Instrumentation Processor Architectures Informatik Ingenieurwissenschaften |
| title | Low power interconnect design |
| title_auth | Low power interconnect design |
| title_exact_search | Low power interconnect design |
| title_full | Low power interconnect design Sandeep Saini |
| title_fullStr | Low power interconnect design Sandeep Saini |
| title_full_unstemmed | Low power interconnect design Sandeep Saini |
| title_short | Low power interconnect design |
| title_sort | low power interconnect design |
| topic | Engineering Computer science Electronics Systems engineering Circuits and Systems Electronics and Microelectronics, Instrumentation Processor Architectures Informatik Ingenieurwissenschaften |
| topic_facet | Engineering Computer science Electronics Systems engineering Circuits and Systems Electronics and Microelectronics, Instrumentation Processor Architectures Informatik Ingenieurwissenschaften |
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