Finite state machines in hardware: theory and design (with VHDL and SystemVerilog)
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Cambridge, Massachusetts
The MIT Press
[2013]
|
| Schlagworte: | |
| Online-Zugang: | FHA01 FHI01 Volltext |
| Beschreibung: | Includes bibliographical references (pages [331]) |
| Beschreibung: | 1 Online-Ressource (x, 337 pages) |
| ISBN: | 0262019663 0262319098 9780262019668 9780262319096 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV042509285 | ||
| 003 | DE-604 | ||
| 005 | 20150417 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 150417s2013 |||| o||u| ||||||eng d | ||
| 020 | |a 0262019663 |9 0-262-01966-3 | ||
| 020 | |a 0262319098 |c electronic bk. |9 0-262-31909-8 | ||
| 020 | |a 9780262019668 |9 978-0-262-01966-8 | ||
| 020 | |a 9780262319096 |c electronic bk. |9 978-0-262-31909-6 | ||
| 035 | |a (OCoLC)881431491 | ||
| 035 | |a (DE-599)BVBBV042509285 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-Aug4 |a DE-573 | ||
| 082 | 0 | |a 621.39/2 |2 23 | |
| 100 | 1 | |a Pedroni, Volnei A. |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Finite state machines in hardware |b theory and design (with VHDL and SystemVerilog) |c Volnei A. Pedroni |
| 264 | 1 | |a Cambridge, Massachusetts |b The MIT Press |c [2013] | |
| 300 | |a 1 Online-Ressource (x, 337 pages) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Includes bibliographical references (pages [331]) | ||
| 650 | 4 | |a Datenverarbeitung | |
| 650 | 4 | |a Mathematisches Modell | |
| 650 | 4 | |a SystemVerilog (Computer hardware description language) | |
| 650 | 4 | |a VHDL (Computer hardware description language) | |
| 650 | 4 | |a Sequential machine theory |x Data processing | |
| 650 | 4 | |a Computer systems |x Mathematical models | |
| 650 | 0 | 7 | |a VHDL |0 (DE-588)4254792-1 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VHDL |0 (DE-588)4254792-1 |D s |
| 689 | 0 | 1 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 856 | 4 | 0 | |u http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668 |x Verlag |3 Volltext |
| 912 | |a ZDB-37-IEM | ||
| 940 | 1 | |q ZDB-37-IEM_GB/15 | |
| 999 | |a oai:aleph.bib-bvb.de:BVB01-027943849 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668 |l FHA01 |p ZDB-37-IEM |x Verlag |3 Volltext | |
| 966 | e | |u http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668 |l FHI01 |p ZDB-37-IEM |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804153253658624000 |
|---|---|
| any_adam_object | |
| author | Pedroni, Volnei A. |
| author_facet | Pedroni, Volnei A. |
| author_role | aut |
| author_sort | Pedroni, Volnei A. |
| author_variant | v a p va vap |
| building | Verbundindex |
| bvnumber | BV042509285 |
| collection | ZDB-37-IEM |
| ctrlnum | (OCoLC)881431491 (DE-599)BVBBV042509285 |
| dewey-full | 621.39/2 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.39/2 |
| dewey-search | 621.39/2 |
| dewey-sort | 3621.39 12 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>02092nmm a2200517zc 4500</leader><controlfield tag="001">BV042509285</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20150417 </controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">150417s2013 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0262019663</subfield><subfield code="9">0-262-01966-3</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">0262319098</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">0-262-31909-8</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780262019668</subfield><subfield code="9">978-0-262-01966-8</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9780262319096</subfield><subfield code="c">electronic bk.</subfield><subfield code="9">978-0-262-31909-6</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)881431491</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV042509285</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-Aug4</subfield><subfield code="a">DE-573</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.39/2</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Pedroni, Volnei A.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Finite state machines in hardware</subfield><subfield code="b">theory and design (with VHDL and SystemVerilog)</subfield><subfield code="c">Volnei A. Pedroni</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cambridge, Massachusetts</subfield><subfield code="b">The MIT Press</subfield><subfield code="c">[2013]</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (x, 337 pages)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references (pages [331])</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Datenverarbeitung</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Mathematisches Modell</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">SystemVerilog (Computer hardware description language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">VHDL (Computer hardware description language)</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Sequential machine theory</subfield><subfield code="x">Data processing</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer systems</subfield><subfield code="x">Mathematical models</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VHDL</subfield><subfield code="0">(DE-588)4254792-1</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-37-IEM</subfield></datafield><datafield tag="940" ind1="1" ind2=" "><subfield code="q">ZDB-37-IEM_GB/15</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027943849</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668</subfield><subfield code="l">FHA01</subfield><subfield code="p">ZDB-37-IEM</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-37-IEM</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV042509285 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:23:40Z |
| institution | BVB |
| isbn | 0262019663 0262319098 9780262019668 9780262319096 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027943849 |
| oclc_num | 881431491 |
| open_access_boolean | |
| owner | DE-Aug4 DE-573 |
| owner_facet | DE-Aug4 DE-573 |
| physical | 1 Online-Ressource (x, 337 pages) |
| psigel | ZDB-37-IEM ZDB-37-IEM_GB/15 |
| publishDate | 2013 |
| publishDateSearch | 2013 |
| publishDateSort | 2013 |
| publisher | The MIT Press |
| record_format | marc |
| spelling | Pedroni, Volnei A. Verfasser aut Finite state machines in hardware theory and design (with VHDL and SystemVerilog) Volnei A. Pedroni Cambridge, Massachusetts The MIT Press [2013] 1 Online-Ressource (x, 337 pages) txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references (pages [331]) Datenverarbeitung Mathematisches Modell SystemVerilog (Computer hardware description language) VHDL (Computer hardware description language) Sequential machine theory Data processing Computer systems Mathematical models VHDL (DE-588)4254792-1 gnd rswk-swf VERILOG (DE-588)4268385-3 gnd rswk-swf VHDL (DE-588)4254792-1 s VERILOG (DE-588)4268385-3 s 1\p DE-604 http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Pedroni, Volnei A. Finite state machines in hardware theory and design (with VHDL and SystemVerilog) Datenverarbeitung Mathematisches Modell SystemVerilog (Computer hardware description language) VHDL (Computer hardware description language) Sequential machine theory Data processing Computer systems Mathematical models VHDL (DE-588)4254792-1 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4254792-1 (DE-588)4268385-3 |
| title | Finite state machines in hardware theory and design (with VHDL and SystemVerilog) |
| title_auth | Finite state machines in hardware theory and design (with VHDL and SystemVerilog) |
| title_exact_search | Finite state machines in hardware theory and design (with VHDL and SystemVerilog) |
| title_full | Finite state machines in hardware theory and design (with VHDL and SystemVerilog) Volnei A. Pedroni |
| title_fullStr | Finite state machines in hardware theory and design (with VHDL and SystemVerilog) Volnei A. Pedroni |
| title_full_unstemmed | Finite state machines in hardware theory and design (with VHDL and SystemVerilog) Volnei A. Pedroni |
| title_short | Finite state machines in hardware |
| title_sort | finite state machines in hardware theory and design with vhdl and systemverilog |
| title_sub | theory and design (with VHDL and SystemVerilog) |
| topic | Datenverarbeitung Mathematisches Modell SystemVerilog (Computer hardware description language) VHDL (Computer hardware description language) Sequential machine theory Data processing Computer systems Mathematical models VHDL (DE-588)4254792-1 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Datenverarbeitung Mathematisches Modell SystemVerilog (Computer hardware description language) VHDL (Computer hardware description language) Sequential machine theory Data processing Computer systems Mathematical models VHDL VERILOG |
| url | http://ieeexplore.ieee.org/xpl/bkabstractplus.jsp?bkn=6712668 |
| work_keys_str_mv | AT pedronivolneia finitestatemachinesinhardwaretheoryanddesignwithvhdlandsystemverilog |