Resilient cross-layer design of digital integrated circuits:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Abschlussarbeit Buch |
| Sprache: | English |
| Veröffentlicht: |
München
Verl. Dr. Hut
2015
|
| Ausgabe: | 1. Aufl. |
| Schriftenreihe: | Elektrotechnik
|
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | 139 S. graph. Darst. |
| ISBN: | 9783843919838 |
Internformat
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Datensatz im Suchindex
| _version_ | 1804153042236342272 |
|---|---|
| adam_text | CONTENTS
1 RELIABILITY IN INTEGRATED CIRCUITS 1
1.1 HIERARCHICAL SYSTEM DESIGN 4
1.2 RESILIENCE ARTICULATION POINT 6
1.2.1 DESIGN PARAMETERS V 8
1.2.2 ENVIRONMENTAL AND OPERATING CONDITIONS 8
1.2.3 CORRELATED (ERROR) STATES S 8
1.2.4 THE ERROR FUNCTION 7 9
1.2.5 COMPLETE FLOW 9
1.2.6 RELATION TO THE STATE OF THE AN 10
1.3 OUTLINE 11
1.3.1 CONTRIBUTIONS 11
1.3.2 PUBLICATIONS 12
1.3.3 STRUCTURE 14
2 FAULTS AND FAULT-INSENSITIVE DESIGN 15
2.1 MANUFACTURING VARIATIONS 16
2.1.1 GLOBAL PROCESS VARIATIONS 16
2.1.2 LOCAL PROCESS VARIATIONS 18
2.2 AGING 21
2.2.1 NEGATIVE BIAS TEMPERATURE INSTABILITY 21
2.2.2 COMPARISON TO THE STATE OF THE ART 25
2.3 INTRINSIC NOISE 27
2.3.1 COMPARISON TO THE STATE OF THE ART 30
2.3.2 EXPERIMENTAL RESULTS 31
2.4 PARTICLE STRIKES 33
2.5 CIRCUIT PERFORMANCES 36
3 MODELING OF ERRORS AND THEIR DEPENDENCIES 45
3.1 SOFT ERRORS 47
3.1.1 BIT UPSETS INDUCED BY INTRINSIC NOISE 47
3.1.2 BIT UPSETS INDUCED BY PARTICLE STRIKES 49
3.2 PARAMETRIC ERRORS 52
3.2.1 LOGIC 53
HTTP://D-NB.INFO/1067206280
CONTENTS
3.3 WORKLOAD 62
3.3.1 COMPUTATION OF SIGNAL PROBABILITIES 63
3.3.2 COMPARISON TO THE STATE OF THE ART 69
3.3.3 EXPERIMENTAL RESULTS 71
3.4 VARIATION IN USAGE PROFILES 76
3.4.1 EXPERIMENTAL RESULTS 81
3.5 CONTROL-LEVEL IMPACT 85
3.5.1 PROPAGATION RULES 86
ONE INPUT IS CONSTANT AT LOGIC ZERO OR ONE 87
BOTH INPUTS ARE RISING OR FALLING 88
INPUT A IS UNKNOWN (
JC
) AND INPUT B IS RISING OR FALLING .... 89
INPUT A IS RISING OR FALLING AND INPUT B IS UNKNOWN (X) .... 89
3.5.2 EXAMPLE: 2-INPUT NAND CELL 93
3.5.3 EXPERIMENTAL RESULTS 94
4 SYSTEM FAILURE ANALYSIS 97
4.1 FAULT INJECTION 97
4.2 STATISTICAL INFERENCE 99
4.2.1 SAMPLING DISTRIBUTIONS 99
PARAMETER SCALING 100
PARAMETER TRANSLATION 100
MIXTURE DISTRIBUTIONS 101
4.2.2 ESTIMATORS 102
INTEGRATION ESTIMATOR 104
RATIO ESTIMATOR 104
4.2.3 OPTIMAL PARAMETER ESTIMATION 105
4.2.4 EXAMPLE 106
4.3 DEMONSTRATION SYSTEM 108
4.4 SINGLE EVENT UPSETS IN THE DATA CACHE 110
4.4.1 DISTRIBUTION SCALING PARAMETERS 110
4.4.2 QUANTITATIVE ANALYSIS 110
4.4.3 QUALITATIVE ANALYSIS 112
4.4.4 TVADE-OFF ANALYSIS 113
5 CONCLUSION 115
A TECHNOLOGY CHARACTERISTICS 117
A.1 PLANAR CMOS 117
A.2 FINFETCMOS 118
A.3 METAL GATE WORK FUNCTION VARIABILITY 119
BIBLIOGRAPHY 121
LIST OF FIGURES
LIST OF TABLES
CONTENTS
135
139
|
| any_adam_object | 1 |
| author | Kleeberger, Veit B. |
| author_facet | Kleeberger, Veit B. |
| author_role | aut |
| author_sort | Kleeberger, Veit B. |
| author_variant | v b k vb vbk |
| building | Verbundindex |
| bvnumber | BV042392377 |
| classification_tum | ELT 272d |
| ctrlnum | (OCoLC)904450380 (DE-599)BVBBV042392377 |
| discipline | Elektrotechnik |
| edition | 1. Aufl. |
| format | Thesis Book |
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| indexdate | 2024-07-10T01:20:19Z |
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| isbn | 9783843919838 |
| language | English |
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| series2 | Elektrotechnik |
| spelling | Kleeberger, Veit B. Verfasser aut Resilient cross-layer design of digital integrated circuits Veit Benedikt Kleeberger 1. Aufl. München Verl. Dr. Hut 2015 139 S. graph. Darst. txt rdacontent n rdamedia nc rdacarrier Elektrotechnik Zugl.: München, Techn. Univ., Diss., 2014 Computersimulation (DE-588)4148259-1 gnd rswk-swf Fehlermodell (DE-588)4380447-0 gnd rswk-swf Zuverlässigkeit (DE-588)4059245-5 gnd rswk-swf Schaltungsanalyse (DE-588)4179387-0 gnd rswk-swf Fertigungsfehler (DE-588)4286623-6 gnd rswk-swf Entwurfsautomation (DE-588)4312536-0 gnd rswk-swf Eingebettetes System (DE-588)4396978-1 gnd rswk-swf Hierarchisches System (DE-588)4159833-7 gnd rswk-swf Systementwurf (DE-588)4261480-6 gnd rswk-swf Digitale integrierte Schaltung (DE-588)4113313-4 gnd rswk-swf (DE-588)4113937-9 Hochschulschrift gnd-content Digitale integrierte Schaltung (DE-588)4113313-4 s Entwurfsautomation (DE-588)4312536-0 s Zuverlässigkeit (DE-588)4059245-5 s Fehlermodell (DE-588)4380447-0 s Fertigungsfehler (DE-588)4286623-6 s Schaltungsanalyse (DE-588)4179387-0 s Hierarchisches System (DE-588)4159833-7 s Systementwurf (DE-588)4261480-6 s Computersimulation (DE-588)4148259-1 s Eingebettetes System (DE-588)4396978-1 s DE-604 DNB Datenaustausch application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027828239&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis |
| spellingShingle | Kleeberger, Veit B. Resilient cross-layer design of digital integrated circuits Computersimulation (DE-588)4148259-1 gnd Fehlermodell (DE-588)4380447-0 gnd Zuverlässigkeit (DE-588)4059245-5 gnd Schaltungsanalyse (DE-588)4179387-0 gnd Fertigungsfehler (DE-588)4286623-6 gnd Entwurfsautomation (DE-588)4312536-0 gnd Eingebettetes System (DE-588)4396978-1 gnd Hierarchisches System (DE-588)4159833-7 gnd Systementwurf (DE-588)4261480-6 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd |
| subject_GND | (DE-588)4148259-1 (DE-588)4380447-0 (DE-588)4059245-5 (DE-588)4179387-0 (DE-588)4286623-6 (DE-588)4312536-0 (DE-588)4396978-1 (DE-588)4159833-7 (DE-588)4261480-6 (DE-588)4113313-4 (DE-588)4113937-9 |
| title | Resilient cross-layer design of digital integrated circuits |
| title_auth | Resilient cross-layer design of digital integrated circuits |
| title_exact_search | Resilient cross-layer design of digital integrated circuits |
| title_full | Resilient cross-layer design of digital integrated circuits Veit Benedikt Kleeberger |
| title_fullStr | Resilient cross-layer design of digital integrated circuits Veit Benedikt Kleeberger |
| title_full_unstemmed | Resilient cross-layer design of digital integrated circuits Veit Benedikt Kleeberger |
| title_short | Resilient cross-layer design of digital integrated circuits |
| title_sort | resilient cross layer design of digital integrated circuits |
| topic | Computersimulation (DE-588)4148259-1 gnd Fehlermodell (DE-588)4380447-0 gnd Zuverlässigkeit (DE-588)4059245-5 gnd Schaltungsanalyse (DE-588)4179387-0 gnd Fertigungsfehler (DE-588)4286623-6 gnd Entwurfsautomation (DE-588)4312536-0 gnd Eingebettetes System (DE-588)4396978-1 gnd Hierarchisches System (DE-588)4159833-7 gnd Systementwurf (DE-588)4261480-6 gnd Digitale integrierte Schaltung (DE-588)4113313-4 gnd |
| topic_facet | Computersimulation Fehlermodell Zuverlässigkeit Schaltungsanalyse Fertigungsfehler Entwurfsautomation Eingebettetes System Hierarchisches System Systementwurf Digitale integrierte Schaltung Hochschulschrift |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027828239&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
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