ASIC and FPGA verification: a guide to component modeling
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
San Francisco, Calif.
Morgan Kaufmann
2004
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Online-Zugang: | FAW01 Volltext |
| Beschreibung: | Includes index Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification |
| Beschreibung: | 1 Online-Ressource (xx, 316 p.) |
| ISBN: | 0125105819 9780125105811 |
Internformat
MARC
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| 650 | 4 | |a Circuits intégrés à la demande | |
| 650 | 4 | |a Réseaux logiques programmables par l'utilisateur | |
| 650 | 7 | |a Application-specific integrated circuits |2 fast | |
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Datensatz im Suchindex
| _version_ | 1804152892905488384 |
|---|---|
| any_adam_object | |
| author | Munden, Richard |
| author_facet | Munden, Richard |
| author_role | aut |
| author_sort | Munden, Richard |
| author_variant | r m rm |
| building | Verbundindex |
| bvnumber | BV042307519 |
| collection | ZDB-33-ESD |
| ctrlnum | (OCoLC)56837419 (DE-599)BVBBV042307519 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV042307519 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:17:56Z |
| institution | BVB |
| isbn | 0125105819 9780125105811 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027744511 |
| oclc_num | 56837419 |
| open_access_boolean | |
| owner | DE-1046 |
| owner_facet | DE-1046 |
| physical | 1 Online-Ressource (xx, 316 p.) |
| psigel | ZDB-33-ESD FLA_PDA_ESD ZDB-33-ESD FAW_PDA_ESD |
| publishDate | 2004 |
| publishDateSearch | 2004 |
| publishDateSort | 2004 |
| publisher | Morgan Kaufmann |
| record_format | marc |
| series2 | Morgan Kaufmann series in systems on silicon |
| spelling | Munden, Richard Verfasser aut ASIC and FPGA verification a guide to component modeling Richard Munden San Francisco, Calif. Morgan Kaufmann 2004 1 Online-Ressource (xx, 316 p.) txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon Includes index Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification Circuits intégrés à la demande Réseaux logiques programmables par l'utilisateur Application-specific integrated circuits fast Application specific integrated circuits Hierarchische Simulation (DE-588)4426470-7 gnd rswk-swf Verifikation (DE-588)4135577-5 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 gnd rswk-swf Digitalelektronik (DE-588)4260328-6 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf Field programmable gate array (DE-588)4347749-5 gnd rswk-swf Kundenspezifische Schaltung (DE-588)4122250-7 s Field programmable gate array (DE-588)4347749-5 s Hierarchische Simulation (DE-588)4426470-7 s 1\p DE-604 Digitalelektronik (DE-588)4260328-6 s Integrierte Schaltung (DE-588)4027242-4 s Verifikation (DE-588)4135577-5 s 2\p DE-604 http://www.sciencedirect.com/science/book/9780125105811 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk 2\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Munden, Richard ASIC and FPGA verification a guide to component modeling Circuits intégrés à la demande Réseaux logiques programmables par l'utilisateur Application-specific integrated circuits fast Application specific integrated circuits Hierarchische Simulation (DE-588)4426470-7 gnd Verifikation (DE-588)4135577-5 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Digitalelektronik (DE-588)4260328-6 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Field programmable gate array (DE-588)4347749-5 gnd |
| subject_GND | (DE-588)4426470-7 (DE-588)4135577-5 (DE-588)4122250-7 (DE-588)4260328-6 (DE-588)4027242-4 (DE-588)4347749-5 |
| title | ASIC and FPGA verification a guide to component modeling |
| title_auth | ASIC and FPGA verification a guide to component modeling |
| title_exact_search | ASIC and FPGA verification a guide to component modeling |
| title_full | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_fullStr | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_full_unstemmed | ASIC and FPGA verification a guide to component modeling Richard Munden |
| title_short | ASIC and FPGA verification |
| title_sort | asic and fpga verification a guide to component modeling |
| title_sub | a guide to component modeling |
| topic | Circuits intégrés à la demande Réseaux logiques programmables par l'utilisateur Application-specific integrated circuits fast Application specific integrated circuits Hierarchische Simulation (DE-588)4426470-7 gnd Verifikation (DE-588)4135577-5 gnd Kundenspezifische Schaltung (DE-588)4122250-7 gnd Digitalelektronik (DE-588)4260328-6 gnd Integrierte Schaltung (DE-588)4027242-4 gnd Field programmable gate array (DE-588)4347749-5 gnd |
| topic_facet | Circuits intégrés à la demande Réseaux logiques programmables par l'utilisateur Application-specific integrated circuits Application specific integrated circuits Hierarchische Simulation Verifikation Kundenspezifische Schaltung Digitalelektronik Integrierte Schaltung Field programmable gate array |
| url | http://www.sciencedirect.com/science/book/9780125105811 |
| work_keys_str_mv | AT mundenrichard asicandfpgaverificationaguidetocomponentmodeling |