Verification techniques for system-level design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Amsterdam
Morgan Kaufmann Publishers
c2008
|
| Schriftenreihe: | Morgan Kaufmann series in systems on silicon
|
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Beschreibung: | This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology Includes bibliographical references and index |
| Beschreibung: | 1 Online-Ressource (viii, 240 p.) |
| ISBN: | 9780123706164 0123706165 |
Internformat
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| 245 | 1 | 0 | |a Verification techniques for system-level design |c Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| 264 | 1 | |a Amsterdam |b Morgan Kaufmann Publishers |c c2008 | |
| 300 | |a 1 Online-Ressource (viii, 240 p.) | ||
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| 500 | |a This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology | ||
| 500 | |a Includes bibliographical references and index | ||
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| 650 | 4 | |a Formal methods (Computer science) | |
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Datensatz im Suchindex
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|---|---|
| any_adam_object | |
| author | Fujita, Masahiro |
| author_facet | Fujita, Masahiro |
| author_role | aut |
| author_sort | Fujita, Masahiro |
| author_variant | m f mf |
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| bvnumber | BV042305711 |
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| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
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| id | DE-604.BV042305711 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:17:53Z |
| institution | BVB |
| isbn | 9780123706164 0123706165 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027742703 |
| oclc_num | 228148347 182548558 |
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| owner_facet | DE-1046 |
| physical | 1 Online-Ressource (viii, 240 p.) |
| psigel | ZDB-33-ESD ZDB-33-EBS FAW_PDA_ESD FLA_PDA_ESD |
| publishDate | 2008 |
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| publisher | Morgan Kaufmann Publishers |
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| series2 | Morgan Kaufmann series in systems on silicon |
| spelling | Fujita, Masahiro Verfasser aut Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad Amsterdam Morgan Kaufmann Publishers c2008 1 Online-Ressource (viii, 240 p.) txt rdacontent c rdamedia cr rdacarrier Morgan Kaufmann series in systems on silicon This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. Formal verification of high-level designs (RTL or higher). Verification techniques are discussed with associated system-level design methodology Includes bibliographical references and index Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd rswk-swf System-on-Chip (DE-588)4740357-3 gnd rswk-swf LSI (DE-588)4168200-2 gnd rswk-swf System-on-Chip (DE-588)4740357-3 s LSI (DE-588)4168200-2 s Hardwareverifikation (DE-588)4214982-4 s 1\p DE-604 Ghosh, Indradeep Sonstige oth Prasad, Mukul Sonstige oth http://www.sciencedirect.com/science/book/9780123706164 Verlag Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Fujita, Masahiro Verification techniques for system-level design Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd System-on-Chip (DE-588)4740357-3 gnd LSI (DE-588)4168200-2 gnd |
| subject_GND | (DE-588)4214982-4 (DE-588)4740357-3 (DE-588)4168200-2 |
| title | Verification techniques for system-level design |
| title_auth | Verification techniques for system-level design |
| title_exact_search | Verification techniques for system-level design |
| title_full | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_fullStr | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_full_unstemmed | Verification techniques for system-level design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad |
| title_short | Verification techniques for system-level design |
| title_sort | verification techniques for system level design |
| topic | Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) Hardwareverifikation (DE-588)4214982-4 gnd System-on-Chip (DE-588)4740357-3 gnd LSI (DE-588)4168200-2 gnd |
| topic_facet | Systems on a chip Testing Integrated circuits Verification Formal methods (Computer science) Hardwareverifikation System-on-Chip LSI |
| url | http://www.sciencedirect.com/science/book/9780123706164 |
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