Modern processor design: fundamentals of superscalar processors
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Buch |
| Sprache: | English |
| Veröffentlicht: |
Long Grove
Waveland Press
2013
|
| Ausgabe: | reissued |
| Schlagworte: | |
| Online-Zugang: | Inhaltsverzeichnis |
| Beschreibung: | "Reissued by Wavelands Press." - 2005 erschienen bei McGraw-Hill. Includes bibliographical references and index |
| Beschreibung: | xiv, 642 pages Ill., graph. Darst. 24 cm |
| ISBN: | 1478607831 9781478607830 |
Internformat
MARC
| LEADER | 00000nam a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV042187223 | ||
| 003 | DE-604 | ||
| 005 | 20241029 | ||
| 007 | t| | ||
| 008 | 141114s2013 xx ad|| |||| 00||| eng d | ||
| 020 | |a 1478607831 |9 1-4786-0783-1 | ||
| 020 | |a 9781478607830 |9 978-1-4786-0783-0 | ||
| 035 | |a (OCoLC)897750421 | ||
| 035 | |a (DE-599)BVBBV042187223 | ||
| 040 | |a DE-604 |b ger |e rakwb | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-91G |a DE-473 | ||
| 084 | |a ST 170 |0 (DE-625)143602: |2 rvk | ||
| 084 | |a DAT 210f |2 stub | ||
| 100 | 1 | |a Shen, John Paul |e Verfasser |0 (DE-588)172372089 |4 aut | |
| 245 | 1 | 0 | |a Modern processor design |b fundamentals of superscalar processors |c John Paul Shen ; Mikko H. Lipasti |
| 250 | |a reissued | ||
| 264 | 1 | |a Long Grove |b Waveland Press |c 2013 | |
| 300 | |a xiv, 642 pages |b Ill., graph. Darst. |c 24 cm | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b n |2 rdamedia | ||
| 338 | |b nc |2 rdacarrier | ||
| 500 | |a "Reissued by Wavelands Press." - 2005 erschienen bei McGraw-Hill. | ||
| 500 | |a Includes bibliographical references and index | ||
| 650 | 4 | |a Microprocessors / Design and construction | |
| 650 | 0 | 7 | |a Computerarchitektur |0 (DE-588)4048717-9 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mikroprozessor 14500 |0 (DE-588)4405181-5 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a Mikroprozessor |0 (DE-588)4039232-6 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Mikroprozessor |0 (DE-588)4039232-6 |D s |
| 689 | 0 | |5 DE-604 | |
| 689 | 1 | 0 | |a Mikroprozessor 14500 |0 (DE-588)4405181-5 |D s |
| 689 | 1 | |8 1\p |5 DE-604 | |
| 689 | 2 | 0 | |a Computerarchitektur |0 (DE-588)4048717-9 |D s |
| 689 | 2 | |5 DE-604 | |
| 700 | 1 | |a Lipasti, Mikko H. |e Verfasser |4 aut | |
| 856 | 4 | 2 | |m Digitalisierung UB Bamberg - ADAM Catalogue Enrichment |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027626333&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 943 | 1 | |a oai:aleph.bib-bvb.de:BVB01-027626333 | |
Datensatz im Suchindex
| _version_ | 1816445703330725888 |
|---|---|
| adam_text |
Table of Contents About the Authors Preface 1 Processor Design 1.1 The Evolution of Microprocessors 1.2 Instruction Set Processor Design 1.2.1 1.2.2 1.2.3 1.2.4 1.3 Digital Systems Design Architecture, Implementation, and Realization Instruction Set Architecture Dynamic-Static Interface Principles of Processor Performance 1.3.1 1.3.2 1.3.3 Processor Performance Equation Processor Performance Optimizations Performance Evaluation Method 1.4 Instruction-Level Parallel Processing 1.4.1 1.4.2 1.4.3 4 5 6 8 10 10 11 13 16 16 24 27 32 Pipelined Processors 39 2.1 2.2 Pipelining Fundamentals 40 2.1.1 2.1.2 2.1.3 2.1.4 40 44 48 51 2.3 2.4 Pipelined Design Arithmetic Pipeline Example Pipelining Idealism Instruction Pipelining Pipelined Processor Design 2.2.1 2.2.2 2.2.3 2.2.4 3 1 2 4 Summary 1.5 2 From Scalar to Superscalar Limits of Instruction-Level Parallelism Machines for Instruction-Level Parallelism ix x Balancing Pipeline Stages Unifying Instruction Types Minimizing Pipeline Stalls Commercial Pipelined Processors Deeply Pipelined Processors Summary Memory and I/O Systems 3.1 3.2 3.3 Introduction Computer System Overview Key Concepts:Latency and Bandwidth 54 55 61 71 87 94 97 105 105 106 107
3.4 3.5 3.6 3.7 3.8 4 Superscalar Organization 4.1 4.2 4.3 4.4 5 Memory Hierarchy 3.4.1 Components of a Modern Memory Hierarchy 3.4.2 Temporal and Spatial Locality 3.4.3 Caching and Cache Memories 3.4.4 Main Memory Virtual Memory Systems 3.5.1 Demand Paging 3.5.2 Memory Protection 3.5.3 Page Table Architectures Memory Hierarchy Implementation Input/Output Systems 3.7.1 Types of I/O Devices 3.7.2 Computer System Busses 3.7.3 Communication with I/O Devices 3.7.4 Interaction of I/O Devices and Memory Hierarchy Summary Limitations of Scalar Pipelines 4.1.1 Upper Bound on Scalar Pipeline Throughput 4.1.2 Inefficient Unification into a Single Pipeline 4.1.3 Performance Lost Due to a Rigid Pipeline From Scalar to Superscalar Pipelines 4.2.1 Parallel Pipelines 4.2.2 Diversified Pipelines 4.2.3 Dynamic Pipelines Superscalar Pipeline Overview 4.3.1 Instruction Fetching 4.3.2 Instruction Decoding 4.3.3 Instruction Dispatching 4.3.4 Instruction Execution 4.3.5 Instruction Completion and Retiring Summary Superscalar Techniques 5.1 Instruction Flow Techniques 5.1.1 Program Control Flow and Control Dependences 5.1.2 Performance Degradation Due to Branches 5.1.3 Branch Prediction Techniques 5.1.4 Branch Misprediction Recovery 5.1.5 Advanced Branch Prediction Techniques 5.1.6 Other Instruction Flow Techniques 5.2 Register Data Flow Techniques 5.2.1 5.2.2 5.2.3 Register Reuse and False Data Dependences Register Renaming Techniques True Data Dependences and the Data Flow Limit 110 111 113 115 127 136 138 141 142 145 153 154 161 165 168 170 177 178 178 179 179 181 181 184 186 190 191 195 199
203 206 209 217 218 218 219 223 228 231 236 237 237 239 244
5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3 Memory Data Flow Techniques 5.3.1 5.3.2 5.3.3 5.3.4 5.4 The Classic Tomasulo Algorithm Dynamic Execution Core Reservation Stations and Reorder Buffer Dynamic Instruction Scheduler Other Register Data Flow Techniques Memory Accessing Instructions Ordering of Memory Accesses Load Bypassing and Load Forwarding Other Memory Data Flow Techniques Summary The PowerPC 620 6.1 6.2 6.3 6.4 6.5 301 307 309 Branch Prediction Fetching and Speculation Instruction Dispatching 311 6.4.1 6.4.2 6.4.3 311 311 313 Instruction Buffer Dispatch Stalls Dispatch Effectiveness Instruction Execution Issue Stalls Execution Parallelism Execution Latency Instruction Completion Completion Parallelism Cache Effects Conclusions and Observations Bridging to the IBM P0WER3 and P0WER4 Summary 7.1.1 7.3 279 6.3.1 6.3.2 Intel's P6 Microarchitecture 7.1 Introduction 7.2 263 266 267 273 302 305 307 6.6.1 6.6.2 6.7 6.8 6.9 262 Introduction Experimental Framework Instruction Fetching 6.5.1 6.5.2 6.5.3 6.6 246 254 256 260 261 В asics of the P6 Microarchitecture 316 316 317 317 318 318 318 320 322 324 329 330 332 Pipelining 334 7.2.1 7.2.2 7.2.3 334 336 337 In-Order Front-End Pipeline Out-of-Order Core Pipeline Retirement Pipeline The In-Order Front End 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 Instruction Cache and ITLB Branch Prediction Instruction Decoder Register Alias Table Allocator 338 338 341 343 346 353
ΊΑ 7.5 7.6 The Out-of-Order Core Reservation Station 7.4.1 Retirement The Reorder Buffer 7.5.1 Memory Subsystem 7.6.1 7.7 7.8 Memory Access Ordering Load Memory Operations 7.6.2 Basic Store Memory Operations 7.6.3 Deferring Memory Operations 7.6.4 Page Faults 7.6.5 Summary Acknowledgments Survey of Superscalar Processors 8.1 Development of Superscalar Processors Early Advances in Uniprocessor Parallelism: 8.1.1 8.1.2 8.1.3 8.1.4 8.2 8.3 The IBM Stretch First Superscalar Design: The IBM Advanced Computer System Instruction-Level Parallelism Studies By-Products of DAE: The First Multiple-Decoding Implementations IBM Cheetah, Panther, and America Decoupled Microarchitectures Other Efforts in the 1980s Wide Acceptance of Superscalar 8.1.5 8.1.6 8.1.7 8.1.8 A Classification of Recent Designs RISC and CISC Retrofits 8.2.1 8.2.2 Speed Demons: Emphasis on Clock Cycle Time 8.2.3 Brainiacs: Emphasis on IPC Processor Descriptions 8.3.1 Compaq / DEC Alpha 8.3.2 Hewlett-Packard РА-RISC Version 1.0 8.3.3 Hewlett-Packard РА-RISC Version 2.0 8.3.4 IBM POWER Intel i960 8.3.5 8.3.6 Intel IA32—Native Approaches 8.3.7 Intel IA32—Decoupled Approaches 8.3.8 x86-64 8.3.9 MIPS 8.3.10 Motorola 8.3.11 PowerPC—32-bit Architecture 8.3.12 PowerPC—64-bit Architecture 8.3.13 PowerPC-AS 8.3.14 SPARC Version 8 8.3.15 SPARC Version 9 355 355 357 357 361 362 363 363 363 364 364 365 369 369 369 372 377 378 380 380 382 382 384 384 386 386 387 387 392 395 397 402 405 409 417 417 422 424 429 431 432 435
8.4 Verification of Superscalar Processors 8.5 Acknowledgments 9 Advanced Instruction Flow Techniques 9.1 Introduction 9.2 Static Branch Prediction Techniques 9.2.1 9.2.2 9.2.3 9.2.4 Single-Direction Prediction Backwards Taken/Forwards Not-Taken Ball/Larus Heuristics Profiling 9.3 Dynamic Branch Prediction Techniques 9.3.1 9.3.2 9.3.3 Basic Algorithms Interference-Reducing Predictors Predicting with Alternative Contexts 9.4 Hybrid Branch Predictors 439 440 453 453 454 455 456 456 457 458 459 472 482 491 The Tournament Predictor Static Predictor Selection Branch Classification The Multihybrid Predictor Prediction Fusion 491 493 494 495 496 9.5 Other Instruction Flow Issues and Techniques 497 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.5.1 9.5.2 9.5.3 9.5.4 Target Prediction Branch Confidence Prediction High-Bandwidth Fetch Mechanisms High-Frequency Fetch Mechanisms 9.6 Summary 512 10 Advanced Register Data Flow Techniques 10.1 Introduction 10.2 Value Locality and Redundant Execution 10.2.1 10.2.2 10.3 10.4 Causes of Value Locality Quantifying Value Locality 519 519 523 523 525 Exploiting Value Locality without Speculation 527 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 527 529 533 534 535 Memoization Instruction Reuse Basic Block and Trace Reuse Data Flow Region Reuse Concluding Remarks Exploiting Value Locality with Speculation 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.5 497 501 504 509 Summary The Weak Dependence Model Value Prediction The Value Prediction Unit Speculative Execution Using Predicted Values Performance of Value Prediction Concluding Remarks 535 535 536 537 542 551 553 554
11 Executing Multiple Threads 11.1 Introduction 11.2 Synchronizing Shared-Memory Threads 11.3 Introduction to Multiprocessor Systems Fully Shared Memory, Unit Latency, 11.3.1 and Lack of Contention Instantaneous Propagation of Writes 11.3.2 11.3.3 Coherent Shared Memory 11.3.4 Implementing Cache Coherence Multilevel Caches, Inclusion, and Virtual Memory 11.3.5 Memory Consistency 11.3.6 11.3.7 The Coherent Memory Interface 11.3.8 Concluding Remarks 11.4 Explicitly Multithreaded Processors 11.4.1 Chip Multiprocessors 11.4.2 Fine-Grained Multithreading 11.4.3 Coarse-Grained Multithreading 11.4.4 Simultaneous Multithreading 11.5 Implicitly Multithreaded Processors 11.5.1 Resolving Control Dependences 11.5.2 Resolving Register Data Dependences 11.5.3 Resolving Memory Data Dependences 11.5.4 Concluding Remarks 11.6 Executing the Same Thread 11.6.1 Fault Detection 11.6.2 Prefetching 11.6.3 Branch Resolution 11.6.4 Concluding Remarks 11.7 Summary Index 559 559 562 565 566 567 567 571 574 576 581 583 584 584 588 589 592 600 601 605 607 610 610 611 613 614 615 616 623 |
| any_adam_object | 1 |
| author | Shen, John Paul Lipasti, Mikko H. |
| author_GND | (DE-588)172372089 |
| author_facet | Shen, John Paul Lipasti, Mikko H. |
| author_role | aut aut |
| author_sort | Shen, John Paul |
| author_variant | j p s jp jps m h l mh mhl |
| building | Verbundindex |
| bvnumber | BV042187223 |
| classification_rvk | ST 170 |
| classification_tum | DAT 210f |
| ctrlnum | (OCoLC)897750421 (DE-599)BVBBV042187223 |
| discipline | Informatik |
| edition | reissued |
| format | Book |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>00000nam a2200000 c 4500</leader><controlfield tag="001">BV042187223</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">20241029</controlfield><controlfield tag="007">t|</controlfield><controlfield tag="008">141114s2013 xx ad|| |||| 00||| eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1478607831</subfield><subfield code="9">1-4786-0783-1</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781478607830</subfield><subfield code="9">978-1-4786-0783-0</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)897750421</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV042187223</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">rakwb</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-91G</subfield><subfield code="a">DE-473</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 170</subfield><subfield code="0">(DE-625)143602:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">DAT 210f</subfield><subfield code="2">stub</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Shen, John Paul</subfield><subfield code="e">Verfasser</subfield><subfield code="0">(DE-588)172372089</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Modern processor design</subfield><subfield code="b">fundamentals of superscalar processors</subfield><subfield code="c">John Paul Shen ; Mikko H. Lipasti</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">reissued</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Long Grove</subfield><subfield code="b">Waveland Press</subfield><subfield code="c">2013</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">xiv, 642 pages</subfield><subfield code="b">Ill., graph. Darst.</subfield><subfield code="c">24 cm</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">n</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">nc</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">"Reissued by Wavelands Press." - 2005 erschienen bei McGraw-Hill.</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references and index</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Microprocessors / Design and construction</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Computerarchitektur</subfield><subfield code="0">(DE-588)4048717-9</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mikroprozessor 14500</subfield><subfield code="0">(DE-588)4405181-5</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Mikroprozessor</subfield><subfield code="0">(DE-588)4039232-6</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Mikroprozessor</subfield><subfield code="0">(DE-588)4039232-6</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="1" ind2="0"><subfield code="a">Mikroprozessor 14500</subfield><subfield code="0">(DE-588)4405181-5</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="689" ind1="2" ind2="0"><subfield code="a">Computerarchitektur</subfield><subfield code="0">(DE-588)4048717-9</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="2" ind2=" "><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Lipasti, Mikko H.</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Digitalisierung UB Bamberg - ADAM Catalogue Enrichment</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027626333&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="943" ind1="1" ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027626333</subfield></datafield></record></collection> |
| id | DE-604.BV042187223 |
| illustrated | Illustrated |
| indexdate | 2024-11-22T17:46:52Z |
| institution | BVB |
| isbn | 1478607831 9781478607830 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027626333 |
| oclc_num | 897750421 |
| open_access_boolean | |
| owner | DE-91G DE-BY-TUM DE-473 DE-BY-UBG |
| owner_facet | DE-91G DE-BY-TUM DE-473 DE-BY-UBG |
| physical | xiv, 642 pages Ill., graph. Darst. 24 cm |
| publishDate | 2013 |
| publishDateSearch | 2013 |
| publishDateSort | 2013 |
| publisher | Waveland Press |
| record_format | marc |
| spelling | Shen, John Paul Verfasser (DE-588)172372089 aut Modern processor design fundamentals of superscalar processors John Paul Shen ; Mikko H. Lipasti reissued Long Grove Waveland Press 2013 xiv, 642 pages Ill., graph. Darst. 24 cm txt rdacontent n rdamedia nc rdacarrier "Reissued by Wavelands Press." - 2005 erschienen bei McGraw-Hill. Includes bibliographical references and index Microprocessors / Design and construction Computerarchitektur (DE-588)4048717-9 gnd rswk-swf Mikroprozessor 14500 (DE-588)4405181-5 gnd rswk-swf Mikroprozessor (DE-588)4039232-6 gnd rswk-swf Mikroprozessor (DE-588)4039232-6 s DE-604 Mikroprozessor 14500 (DE-588)4405181-5 s 1\p DE-604 Computerarchitektur (DE-588)4048717-9 s Lipasti, Mikko H. Verfasser aut Digitalisierung UB Bamberg - ADAM Catalogue Enrichment application/pdf http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027626333&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA Inhaltsverzeichnis 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Shen, John Paul Lipasti, Mikko H. Modern processor design fundamentals of superscalar processors Microprocessors / Design and construction Computerarchitektur (DE-588)4048717-9 gnd Mikroprozessor 14500 (DE-588)4405181-5 gnd Mikroprozessor (DE-588)4039232-6 gnd |
| subject_GND | (DE-588)4048717-9 (DE-588)4405181-5 (DE-588)4039232-6 |
| title | Modern processor design fundamentals of superscalar processors |
| title_auth | Modern processor design fundamentals of superscalar processors |
| title_exact_search | Modern processor design fundamentals of superscalar processors |
| title_full | Modern processor design fundamentals of superscalar processors John Paul Shen ; Mikko H. Lipasti |
| title_fullStr | Modern processor design fundamentals of superscalar processors John Paul Shen ; Mikko H. Lipasti |
| title_full_unstemmed | Modern processor design fundamentals of superscalar processors John Paul Shen ; Mikko H. Lipasti |
| title_short | Modern processor design |
| title_sort | modern processor design fundamentals of superscalar processors |
| title_sub | fundamentals of superscalar processors |
| topic | Microprocessors / Design and construction Computerarchitektur (DE-588)4048717-9 gnd Mikroprozessor 14500 (DE-588)4405181-5 gnd Mikroprozessor (DE-588)4039232-6 gnd |
| topic_facet | Microprocessors / Design and construction Computerarchitektur Mikroprozessor 14500 Mikroprozessor |
| url | http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027626333&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT shenjohnpaul modernprocessordesignfundamentalsofsuperscalarprocessors AT lipastimikkoh modernprocessordesignfundamentalsofsuperscalarprocessors |