Digital vlsi design with Verilog: a textbook from Silicon Valley Polytechnic Institute
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Cham [u.a.]
Springer
2014
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| Ausgabe: | 2. ed. |
| Schlagworte: | |
| Online-Zugang: | BTU01 FHA01 FHI01 FHN01 FHR01 FKE01 FRO01 FWS01 FWS02 UBY01 Volltext Inhaltsverzeichnis Abstract |
| Beschreibung: | 1 Online-Ressource |
| ISBN: | 9783319047898 |
| DOI: | 10.1007/978-3-319-04789-8 |
Internformat
MARC
| LEADER | 00000nmm a2200000 c 4500 | ||
|---|---|---|---|
| 001 | BV042013867 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 140806s2014 |||| o||u| ||||||eng d | ||
| 020 | |a 9783319047898 |c Online |9 978-3-319-04789-8 | ||
| 024 | 7 | |a 10.1007/978-3-319-04789-8 |2 doi | |
| 035 | |a (OCoLC)882509855 | ||
| 035 | |a (DE-599)BSZ409575089 | ||
| 040 | |a DE-604 |b ger | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-Aug4 |a DE-573 |a DE-859 |a DE-92 |a DE-898 |a DE-634 |a DE-861 |a DE-706 |a DE-863 |a DE-862 | ||
| 050 | 0 | |a TK7888.4 | |
| 082 | 0 | |a 004 | |
| 084 | |a ZN 4904 |0 (DE-625)157419: |2 rvk | ||
| 084 | |a ST 150 |0 (DE-625)143594: |2 rvk | ||
| 084 | |a ST 250 |0 (DE-625)143626: |2 rvk | ||
| 084 | |a ZN 4950 |0 (DE-625)157424: |2 rvk | ||
| 084 | |a TEC008010 |2 sdnb | ||
| 084 | |a TJFC |2 sdnb | ||
| 100 | 1 | |a Williams, John Michael |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Digital vlsi design with Verilog |b a textbook from Silicon Valley Polytechnic Institute |c John Michael Williams |
| 250 | |a 2. ed. | ||
| 264 | 1 | |a Cham [u.a.] |b Springer |c 2014 | |
| 300 | |a 1 Online-Ressource | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 650 | 4 | |a Informatik | |
| 650 | 4 | |a Ingenieurwissenschaften | |
| 650 | 4 | |a Computer science | |
| 650 | 4 | |a Electronics | |
| 650 | 4 | |a Systems engineering | |
| 650 | 4 | |a Engineering | |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VERILOG |0 (DE-588)4268385-3 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | 1 | |a VERILOG |0 (DE-588)4268385-3 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druckausgabe |z 978-3-319-04788-1 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-3-319-04789-8 |x Verlag |3 Volltext |
| 856 | 4 | 2 | |m Springer Fremddatenuebernahme |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027455702&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA |3 Inhaltsverzeichnis |
| 856 | 4 | 2 | |m Springer Fremddatenuebernahme |q application/pdf |u http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027455702&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA |3 Abstract |
| 912 | |a ZDB-2-ENG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-027455702 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l BTU01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l FHA01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l FHI01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l FHN01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l FHR01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l FKE01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l FRO01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l FWS01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l FWS02 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-3-319-04789-8 |l UBY01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
Datensatz im Suchindex
| DE-BY-FWS_katkey | 1015502 |
|---|---|
| _version_ | 1824553635981295616 |
| adam_text | DIGITAL VLSI DESIGN WITH VERILOG
/ WILLIAMS, JOHN MICHAEL
: 2014
TABLE OF CONTENTS / INHALTSVERZEICHNIS
INTRODUCTORY MATERIAL
WEEK 1 CLASS 1
WEEK 1 CLASS 2
WEEK 2 CLASS 1
WEEK 2 CLASS 2
WEEK 3 CLASS 1
WEEK 3 CLASS 2
WEEK 4 CLASS 1
WEEK 4 CLASS 2
WEEK 5 CLASS 1
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WEEK 11CLASS 1
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WEEK 12 CLASS 1
WEEK 12 CLASS 2
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
DIGITAL VLSI DESIGN WITH VERILOG
/ WILLIAMS, JOHN MICHAEL
: 2014
ABSTRACT / INHALTSTEXT
THIS BOOK IS STRUCTURED AS A STEP-BY-STEP COURSE OF STUDY ALONG THE
LINES OF A VLSI INTEGRATED CIRCUIT DESIGN PROJECT. THE ENTIRE VERILOG
LANGUAGE IS PRESENTED, FROM THE BASICS TO EVERYTHING NECESSARY FOR
SYNTHESIS OF AN ENTIRE 70,000 TRANSISTOR, FULL-DUPLEX
SERIALIZER-DESERIALIZER, INCLUDING SYNTHESIZABLE PLLS. THE AUTHOR
INCLUDES EVERYTHING AN ENGINEER NEEDS FOR IN-DEPTH UNDERSTANDING OF THE
VERILOG LANGUAGE: SYNTAX, SYNTHESIS SEMANTICS, SIMULATION, AND TEST.
COMPLETE SOLUTIONS FOR THE 27 LABS ARE PROVIDED IN THE DOWNLOADABLE
FILES THAT ACCOMPANY THE BOOK. FOR READERS WITH ACCESS TO APPROPRIATE
ELECTRONIC DESIGN TOOLS, ALL SOLUTIONS CAN BE DEVELOPED, SIMULATED, AND
SYNTHESIZED AS DESCRIBED IN THE BOOK. A PARTIAL LIST OF DESIGN
TOPICS INCLUDES DESIGN PARTITIONING, HIERARCHY DECOMPOSITION, SAFE
CODING STYLES, BACK ANNOTATION, WRAPPER MODULES, CONCURRENCY, RACE
CONDITIONS, ASSERTION-BASED VERIFICATION, CLOCK SYNCHRONIZATION, AND
DESIGN FOR TEST. A CONCLUDING PRESENTATION OF SPECIAL TOPICS
INCLUDES SYSTEMVERILOG AND VERILOG-AMS. COVERS THE ENTIRE VERILOG
LANGUAGE – USING MOST OF IT IN PRACTICE; PROVIDES 27 LAB EXERCISES,
WITH COMPLETE AND TESTED ANSWERS; EXPLAINS AND EMPHASIZES
SYNTHESIZABILITY, WHEREVER IT PERTAINS TO LANGUAGE FEATURES; DEVELOPS AS
A MAJOR PROJECT A SYNTHESIZABLE 70,000-GATE SERDES; PRESENTS
SYNTHESIS-RELEVANT USAGE OF SYSTEMVERILOG, AND THE BASIC FUNCTIONALITY
OF VERILOG-AMS.
DIESES SCHRIFTSTUECK WURDE MASCHINELL ERZEUGT.
|
| any_adam_object | 1 |
| author | Williams, John Michael |
| author_facet | Williams, John Michael |
| author_role | aut |
| author_sort | Williams, John Michael |
| author_variant | j m w jm jmw |
| building | Verbundindex |
| bvnumber | BV042013867 |
| callnumber-first | T - Technology |
| callnumber-label | TK7888 |
| callnumber-raw | TK7888.4 |
| callnumber-search | TK7888.4 |
| callnumber-sort | TK 47888.4 |
| callnumber-subject | TK - Electrical and Nuclear Engineering |
| classification_rvk | ZN 4904 ST 150 ST 250 ZN 4950 |
| collection | ZDB-2-ENG |
| ctrlnum | (OCoLC)882509855 (DE-599)BSZ409575089 |
| dewey-full | 004 |
| dewey-hundreds | 000 - Computer science, information, general works |
| dewey-ones | 004 - Computer science |
| dewey-raw | 004 |
| dewey-search | 004 |
| dewey-sort | 14 |
| dewey-tens | 000 - Computer science, information, general works |
| discipline | Informatik Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-3-319-04789-8 |
| edition | 2. ed. |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>03328nmm a2200697 c 4500</leader><controlfield tag="001">BV042013867</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">140806s2014 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9783319047898</subfield><subfield code="c">Online</subfield><subfield code="9">978-3-319-04789-8</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-3-319-04789-8</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)882509855</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BSZ409575089</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-Aug4</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-859</subfield><subfield code="a">DE-92</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-634</subfield><subfield code="a">DE-861</subfield><subfield code="a">DE-706</subfield><subfield code="a">DE-863</subfield><subfield code="a">DE-862</subfield></datafield><datafield tag="050" ind1=" " ind2="0"><subfield code="a">TK7888.4</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">004</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4904</subfield><subfield code="0">(DE-625)157419:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 150</subfield><subfield code="0">(DE-625)143594:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ST 250</subfield><subfield code="0">(DE-625)143626:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">ZN 4950</subfield><subfield code="0">(DE-625)157424:</subfield><subfield code="2">rvk</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">TEC008010</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="084" ind1=" " ind2=" "><subfield code="a">TJFC</subfield><subfield code="2">sdnb</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Williams, John Michael</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Digital vlsi design with Verilog</subfield><subfield code="b">a textbook from Silicon Valley Polytechnic Institute</subfield><subfield code="c">John Michael Williams</subfield></datafield><datafield tag="250" ind1=" " ind2=" "><subfield code="a">2. ed.</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Cham [u.a.]</subfield><subfield code="b">Springer</subfield><subfield code="c">2014</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Informatik</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Ingenieurwissenschaften</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer science</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Electronics</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systems engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">VERILOG</subfield><subfield code="0">(DE-588)4268385-3</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druckausgabe</subfield><subfield code="z">978-3-319-04788-1</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Springer Fremddatenuebernahme</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027455702&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Inhaltsverzeichnis</subfield></datafield><datafield tag="856" ind1="4" ind2="2"><subfield code="m">Springer Fremddatenuebernahme</subfield><subfield code="q">application/pdf</subfield><subfield code="u">http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027455702&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA</subfield><subfield code="3">Abstract</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027455702</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">FHA01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">FHR01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">FKE01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">FRO01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">FWS01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">FWS02</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-3-319-04789-8</subfield><subfield code="l">UBY01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV042013867 |
| illustrated | Not Illustrated |
| indexdate | 2025-02-20T06:39:01Z |
| institution | BVB |
| isbn | 9783319047898 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027455702 |
| oclc_num | 882509855 |
| open_access_boolean | |
| owner | DE-Aug4 DE-573 DE-859 DE-92 DE-898 DE-BY-UBR DE-634 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| owner_facet | DE-Aug4 DE-573 DE-859 DE-92 DE-898 DE-BY-UBR DE-634 DE-861 DE-706 DE-863 DE-BY-FWS DE-862 DE-BY-FWS |
| physical | 1 Online-Ressource |
| psigel | ZDB-2-ENG |
| publishDate | 2014 |
| publishDateSearch | 2014 |
| publishDateSort | 2014 |
| publisher | Springer |
| record_format | marc |
| spellingShingle | Williams, John Michael Digital vlsi design with Verilog a textbook from Silicon Valley Polytechnic Institute Informatik Ingenieurwissenschaften Computer science Electronics Systems engineering Engineering VLSI (DE-588)4117388-0 gnd VERILOG (DE-588)4268385-3 gnd |
| subject_GND | (DE-588)4117388-0 (DE-588)4268385-3 |
| title | Digital vlsi design with Verilog a textbook from Silicon Valley Polytechnic Institute |
| title_auth | Digital vlsi design with Verilog a textbook from Silicon Valley Polytechnic Institute |
| title_exact_search | Digital vlsi design with Verilog a textbook from Silicon Valley Polytechnic Institute |
| title_full | Digital vlsi design with Verilog a textbook from Silicon Valley Polytechnic Institute John Michael Williams |
| title_fullStr | Digital vlsi design with Verilog a textbook from Silicon Valley Polytechnic Institute John Michael Williams |
| title_full_unstemmed | Digital vlsi design with Verilog a textbook from Silicon Valley Polytechnic Institute John Michael Williams |
| title_short | Digital vlsi design with Verilog |
| title_sort | digital vlsi design with verilog a textbook from silicon valley polytechnic institute |
| title_sub | a textbook from Silicon Valley Polytechnic Institute |
| topic | Informatik Ingenieurwissenschaften Computer science Electronics Systems engineering Engineering VLSI (DE-588)4117388-0 gnd VERILOG (DE-588)4268385-3 gnd |
| topic_facet | Informatik Ingenieurwissenschaften Computer science Electronics Systems engineering Engineering VLSI VERILOG |
| url | https://doi.org/10.1007/978-3-319-04789-8 http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027455702&sequence=000001&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=027455702&sequence=000003&line_number=0002&func_code=DB_RECORDS&service_type=MEDIA |
| work_keys_str_mv | AT williamsjohnmichael digitalvlsidesignwithverilogatextbookfromsiliconvalleypolytechnicinstitute |