Analysis and design of resilient VLSI circuits: mitigating soft errors and process variations
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
New York
Springer
c2010
|
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Beschreibung: | Includes bibliographical references (p. 283-298) and index |
| Beschreibung: | 1 Online-Ressource (xxii, 212 p.) |
| ISBN: | 1441909311 9781441909312 9781282836815 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV041911740 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 140612s2010 |||| o||u| ||||||eng d | ||
| 020 | |a 1441909311 |c ebook |9 1-4419-0931-1 | ||
| 020 | |a 9781441909312 |c ebook |9 978-1-4419-0931-2 | ||
| 020 | |a 9781282836815 |c MyiLibrary |9 978-1-282-83681-5 | ||
| 035 | |a (OCoLC)778311647 | ||
| 035 | |a (DE-599)BVBBV041911740 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 082 | 0 | |a 621.395 |2 22 | |
| 100 | 1 | |a Garg, Rajesh |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Analysis and design of resilient VLSI circuits |b mitigating soft errors and process variations |c Rajesh Garg, Sunil P. Khatri |
| 264 | 1 | |a New York |b Springer |c c2010 | |
| 300 | |a 1 Online-Ressource (xxii, 212 p.) | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Includes bibliographical references (p. 283-298) and index | ||
| 650 | 4 | |a Integrated circuits / Very large scale integration | |
| 650 | 0 | 7 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |2 gnd |9 rswk-swf |
| 650 | 0 | 7 | |a VLSI |0 (DE-588)4117388-0 |2 gnd |9 rswk-swf |
| 689 | 0 | 0 | |a Integrierte Schaltung |0 (DE-588)4027242-4 |D s |
| 689 | 0 | 1 | |a VLSI |0 (DE-588)4117388-0 |D s |
| 689 | 0 | |8 1\p |5 DE-604 | |
| 700 | 1 | |a Khatri, Sunil P. |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe, Hardcover |z 1-4419-0930-3 |
| 776 | 0 | 8 | |i Erscheint auch als |n Druck-Ausgabe, Hardcover |z 978-1-4419-0930-5 |
| 856 | 4 | 0 | |u http://lib.myilibrary.com?id=283681 |x Aggregator |3 Volltext |
| 912 | |a ZDB-26-MYL | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-027355409 | ||
| 883 | 1 | |8 1\p |a cgwrk |d 20201028 |q DE-101 |u https://d-nb.info/provenance/plan#cgwrk | |
Datensatz im Suchindex
| _version_ | 1804152274720653312 |
|---|---|
| any_adam_object | |
| author | Garg, Rajesh |
| author_facet | Garg, Rajesh |
| author_role | aut |
| author_sort | Garg, Rajesh |
| author_variant | r g rg |
| building | Verbundindex |
| bvnumber | BV041911740 |
| collection | ZDB-26-MYL |
| ctrlnum | (OCoLC)778311647 (DE-599)BVBBV041911740 |
| dewey-full | 621.395 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.395 |
| dewey-search | 621.395 |
| dewey-sort | 3621.395 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>01710nmm a2200433zc 4500</leader><controlfield tag="001">BV041911740</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">140612s2010 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">1441909311</subfield><subfield code="c">ebook</subfield><subfield code="9">1-4419-0931-1</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781441909312</subfield><subfield code="c">ebook</subfield><subfield code="9">978-1-4419-0931-2</subfield></datafield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781282836815</subfield><subfield code="c">MyiLibrary</subfield><subfield code="9">978-1-282-83681-5</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)778311647</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV041911740</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.395</subfield><subfield code="2">22</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Garg, Rajesh</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Analysis and design of resilient VLSI circuits</subfield><subfield code="b">mitigating soft errors and process variations</subfield><subfield code="c">Rajesh Garg, Sunil P. Khatri</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">New York</subfield><subfield code="b">Springer</subfield><subfield code="c">c2010</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource (xxii, 212 p.)</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Includes bibliographical references (p. 283-298) and index</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Integrated circuits / Very large scale integration</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="650" ind1="0" ind2="7"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="2">gnd</subfield><subfield code="9">rswk-swf</subfield></datafield><datafield tag="689" ind1="0" ind2="0"><subfield code="a">Integrierte Schaltung</subfield><subfield code="0">(DE-588)4027242-4</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2="1"><subfield code="a">VLSI</subfield><subfield code="0">(DE-588)4117388-0</subfield><subfield code="D">s</subfield></datafield><datafield tag="689" ind1="0" ind2=" "><subfield code="8">1\p</subfield><subfield code="5">DE-604</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Khatri, Sunil P.</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe, Hardcover</subfield><subfield code="z">1-4419-0930-3</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druck-Ausgabe, Hardcover</subfield><subfield code="z">978-1-4419-0930-5</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">http://lib.myilibrary.com?id=283681</subfield><subfield code="x">Aggregator</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-26-MYL</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027355409</subfield></datafield><datafield tag="883" ind1="1" ind2=" "><subfield code="8">1\p</subfield><subfield code="a">cgwrk</subfield><subfield code="d">20201028</subfield><subfield code="q">DE-101</subfield><subfield code="u">https://d-nb.info/provenance/plan#cgwrk</subfield></datafield></record></collection> |
| id | DE-604.BV041911740 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:08:07Z |
| institution | BVB |
| isbn | 1441909311 9781441909312 9781282836815 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027355409 |
| oclc_num | 778311647 |
| open_access_boolean | |
| physical | 1 Online-Ressource (xxii, 212 p.) |
| psigel | ZDB-26-MYL |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Springer |
| record_format | marc |
| spelling | Garg, Rajesh Verfasser aut Analysis and design of resilient VLSI circuits mitigating soft errors and process variations Rajesh Garg, Sunil P. Khatri New York Springer c2010 1 Online-Ressource (xxii, 212 p.) txt rdacontent c rdamedia cr rdacarrier Includes bibliographical references (p. 283-298) and index Integrated circuits / Very large scale integration Integrierte Schaltung (DE-588)4027242-4 gnd rswk-swf VLSI (DE-588)4117388-0 gnd rswk-swf Integrierte Schaltung (DE-588)4027242-4 s VLSI (DE-588)4117388-0 s 1\p DE-604 Khatri, Sunil P. Sonstige oth Erscheint auch als Druck-Ausgabe, Hardcover 1-4419-0930-3 Erscheint auch als Druck-Ausgabe, Hardcover 978-1-4419-0930-5 http://lib.myilibrary.com?id=283681 Aggregator Volltext 1\p cgwrk 20201028 DE-101 https://d-nb.info/provenance/plan#cgwrk |
| spellingShingle | Garg, Rajesh Analysis and design of resilient VLSI circuits mitigating soft errors and process variations Integrated circuits / Very large scale integration Integrierte Schaltung (DE-588)4027242-4 gnd VLSI (DE-588)4117388-0 gnd |
| subject_GND | (DE-588)4027242-4 (DE-588)4117388-0 |
| title | Analysis and design of resilient VLSI circuits mitigating soft errors and process variations |
| title_auth | Analysis and design of resilient VLSI circuits mitigating soft errors and process variations |
| title_exact_search | Analysis and design of resilient VLSI circuits mitigating soft errors and process variations |
| title_full | Analysis and design of resilient VLSI circuits mitigating soft errors and process variations Rajesh Garg, Sunil P. Khatri |
| title_fullStr | Analysis and design of resilient VLSI circuits mitigating soft errors and process variations Rajesh Garg, Sunil P. Khatri |
| title_full_unstemmed | Analysis and design of resilient VLSI circuits mitigating soft errors and process variations Rajesh Garg, Sunil P. Khatri |
| title_short | Analysis and design of resilient VLSI circuits |
| title_sort | analysis and design of resilient vlsi circuits mitigating soft errors and process variations |
| title_sub | mitigating soft errors and process variations |
| topic | Integrated circuits / Very large scale integration Integrierte Schaltung (DE-588)4027242-4 gnd VLSI (DE-588)4117388-0 gnd |
| topic_facet | Integrated circuits / Very large scale integration Integrierte Schaltung VLSI |
| url | http://lib.myilibrary.com?id=283681 |
| work_keys_str_mv | AT gargrajesh analysisanddesignofresilientvlsicircuitsmitigatingsofterrorsandprocessvariations AT khatrisunilp analysisanddesignofresilientvlsicircuitsmitigatingsofterrorsandprocessvariations |