Minimizing and Exploiting Leakage in VLSI Design:
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Elektronisch E-Book |
| Sprache: | English |
| Veröffentlicht: |
Boston, MA
Springer US
2010
|
| Schlagworte: | |
| Online-Zugang: | BTU01 FHI01 FHN01 FHR01 Volltext |
| Beschreibung: | Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes) |
| Beschreibung: | 1 Online-Ressource |
| ISBN: | 9781441909503 |
| DOI: | 10.1007/978-1-4419-0950-3 |
Internformat
MARC
| LEADER | 00000nmm a2200000zc 4500 | ||
|---|---|---|---|
| 001 | BV041889575 | ||
| 003 | DE-604 | ||
| 005 | 00000000000000.0 | ||
| 007 | cr|uuu---uuuuu | ||
| 008 | 140603s2010 |||| o||u| ||||||eng d | ||
| 020 | |a 9781441909503 |c Online |9 978-1-4419-0950-3 | ||
| 024 | 7 | |a 10.1007/978-1-4419-0950-3 |2 doi | |
| 035 | |a (OCoLC)881655661 | ||
| 035 | |a (DE-599)BVBBV041889575 | ||
| 040 | |a DE-604 |b ger |e aacr | ||
| 041 | 0 | |a eng | |
| 049 | |a DE-634 |a DE-898 |a DE-573 |a DE-92 |a DE-83 | ||
| 082 | 0 | |a 621.3815 |2 23 | |
| 100 | 1 | |a Jayakumar, Nikhil |e Verfasser |4 aut | |
| 245 | 1 | 0 | |a Minimizing and Exploiting Leakage in VLSI Design |c by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri |
| 264 | 1 | |a Boston, MA |b Springer US |c 2010 | |
| 300 | |a 1 Online-Ressource | ||
| 336 | |b txt |2 rdacontent | ||
| 337 | |b c |2 rdamedia | ||
| 338 | |b cr |2 rdacarrier | ||
| 500 | |a Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. | ||
| 500 | |a The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. | ||
| 500 | |a In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes) | ||
| 505 | 0 | |a Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results | |
| 650 | 4 | |a Engineering | |
| 650 | 4 | |a Computer aided design | |
| 650 | 4 | |a Systems engineering | |
| 650 | 4 | |a Circuits and Systems | |
| 650 | 4 | |a Computer-Aided Engineering (CAD, CAE) and Design | |
| 650 | 4 | |a Ingenieurwissenschaften | |
| 700 | 1 | |a Paul, Suganth |e Sonstige |4 oth | |
| 700 | 1 | |a Garg, Rajesh |e Sonstige |4 oth | |
| 700 | 1 | |a Gulati, Kanupriya |e Sonstige |4 oth | |
| 700 | 1 | |a Khatri, Sunil P. |e Sonstige |4 oth | |
| 776 | 0 | 8 | |i Erscheint auch als |n Druckausgabe |z 978-1-4419-0949-7 |
| 856 | 4 | 0 | |u https://doi.org/10.1007/978-1-4419-0950-3 |x Verlag |3 Volltext |
| 912 | |a ZDB-2-ENG | ||
| 999 | |a oai:aleph.bib-bvb.de:BVB01-027333528 | ||
| 966 | e | |u https://doi.org/10.1007/978-1-4419-0950-3 |l BTU01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-1-4419-0950-3 |l FHI01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-1-4419-0950-3 |l FHN01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
| 966 | e | |u https://doi.org/10.1007/978-1-4419-0950-3 |l FHR01 |p ZDB-2-ENG |x Verlag |3 Volltext | |
Datensatz im Suchindex
| _version_ | 1804152238557364224 |
|---|---|
| any_adam_object | |
| author | Jayakumar, Nikhil |
| author_facet | Jayakumar, Nikhil |
| author_role | aut |
| author_sort | Jayakumar, Nikhil |
| author_variant | n j nj |
| building | Verbundindex |
| bvnumber | BV041889575 |
| collection | ZDB-2-ENG |
| contents | Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results |
| ctrlnum | (OCoLC)881655661 (DE-599)BVBBV041889575 |
| dewey-full | 621.3815 |
| dewey-hundreds | 600 - Technology (Applied sciences) |
| dewey-ones | 621 - Applied physics |
| dewey-raw | 621.3815 |
| dewey-search | 621.3815 |
| dewey-sort | 3621.3815 |
| dewey-tens | 620 - Engineering and allied operations |
| discipline | Elektrotechnik / Elektronik / Nachrichtentechnik |
| doi_str_mv | 10.1007/978-1-4419-0950-3 |
| format | Electronic eBook |
| fullrecord | <?xml version="1.0" encoding="UTF-8"?><collection xmlns="http://www.loc.gov/MARC21/slim"><record><leader>05284nmm a2200529zc 4500</leader><controlfield tag="001">BV041889575</controlfield><controlfield tag="003">DE-604</controlfield><controlfield tag="005">00000000000000.0</controlfield><controlfield tag="007">cr|uuu---uuuuu</controlfield><controlfield tag="008">140603s2010 |||| o||u| ||||||eng d</controlfield><datafield tag="020" ind1=" " ind2=" "><subfield code="a">9781441909503</subfield><subfield code="c">Online</subfield><subfield code="9">978-1-4419-0950-3</subfield></datafield><datafield tag="024" ind1="7" ind2=" "><subfield code="a">10.1007/978-1-4419-0950-3</subfield><subfield code="2">doi</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(OCoLC)881655661</subfield></datafield><datafield tag="035" ind1=" " ind2=" "><subfield code="a">(DE-599)BVBBV041889575</subfield></datafield><datafield tag="040" ind1=" " ind2=" "><subfield code="a">DE-604</subfield><subfield code="b">ger</subfield><subfield code="e">aacr</subfield></datafield><datafield tag="041" ind1="0" ind2=" "><subfield code="a">eng</subfield></datafield><datafield tag="049" ind1=" " ind2=" "><subfield code="a">DE-634</subfield><subfield code="a">DE-898</subfield><subfield code="a">DE-573</subfield><subfield code="a">DE-92</subfield><subfield code="a">DE-83</subfield></datafield><datafield tag="082" ind1="0" ind2=" "><subfield code="a">621.3815</subfield><subfield code="2">23</subfield></datafield><datafield tag="100" ind1="1" ind2=" "><subfield code="a">Jayakumar, Nikhil</subfield><subfield code="e">Verfasser</subfield><subfield code="4">aut</subfield></datafield><datafield tag="245" ind1="1" ind2="0"><subfield code="a">Minimizing and Exploiting Leakage in VLSI Design</subfield><subfield code="c">by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri</subfield></datafield><datafield tag="264" ind1=" " ind2="1"><subfield code="a">Boston, MA</subfield><subfield code="b">Springer US</subfield><subfield code="c">2010</subfield></datafield><datafield tag="300" ind1=" " ind2=" "><subfield code="a">1 Online-Ressource</subfield></datafield><datafield tag="336" ind1=" " ind2=" "><subfield code="b">txt</subfield><subfield code="2">rdacontent</subfield></datafield><datafield tag="337" ind1=" " ind2=" "><subfield code="b">c</subfield><subfield code="2">rdamedia</subfield></datafield><datafield tag="338" ind1=" " ind2=" "><subfield code="b">cr</subfield><subfield code="2">rdacarrier</subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. </subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. </subfield></datafield><datafield tag="500" ind1=" " ind2=" "><subfield code="a">In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes)</subfield></datafield><datafield tag="505" ind1="0" ind2=" "><subfield code="a">Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer aided design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Systems engineering</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Circuits and Systems</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Computer-Aided Engineering (CAD, CAE) and Design</subfield></datafield><datafield tag="650" ind1=" " ind2="4"><subfield code="a">Ingenieurwissenschaften</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Paul, Suganth</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Garg, Rajesh</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Gulati, Kanupriya</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="700" ind1="1" ind2=" "><subfield code="a">Khatri, Sunil P.</subfield><subfield code="e">Sonstige</subfield><subfield code="4">oth</subfield></datafield><datafield tag="776" ind1="0" ind2="8"><subfield code="i">Erscheint auch als</subfield><subfield code="n">Druckausgabe</subfield><subfield code="z">978-1-4419-0949-7</subfield></datafield><datafield tag="856" ind1="4" ind2="0"><subfield code="u">https://doi.org/10.1007/978-1-4419-0950-3</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="912" ind1=" " ind2=" "><subfield code="a">ZDB-2-ENG</subfield></datafield><datafield tag="999" ind1=" " ind2=" "><subfield code="a">oai:aleph.bib-bvb.de:BVB01-027333528</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4419-0950-3</subfield><subfield code="l">BTU01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4419-0950-3</subfield><subfield code="l">FHI01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4419-0950-3</subfield><subfield code="l">FHN01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield><datafield tag="966" ind1="e" ind2=" "><subfield code="u">https://doi.org/10.1007/978-1-4419-0950-3</subfield><subfield code="l">FHR01</subfield><subfield code="p">ZDB-2-ENG</subfield><subfield code="x">Verlag</subfield><subfield code="3">Volltext</subfield></datafield></record></collection> |
| id | DE-604.BV041889575 |
| illustrated | Not Illustrated |
| indexdate | 2024-07-10T01:07:32Z |
| institution | BVB |
| isbn | 9781441909503 |
| language | English |
| oai_aleph_id | oai:aleph.bib-bvb.de:BVB01-027333528 |
| oclc_num | 881655661 |
| open_access_boolean | |
| owner | DE-634 DE-898 DE-BY-UBR DE-573 DE-92 DE-83 |
| owner_facet | DE-634 DE-898 DE-BY-UBR DE-573 DE-92 DE-83 |
| physical | 1 Online-Ressource |
| psigel | ZDB-2-ENG |
| publishDate | 2010 |
| publishDateSearch | 2010 |
| publishDateSort | 2010 |
| publisher | Springer US |
| record_format | marc |
| spelling | Jayakumar, Nikhil Verfasser aut Minimizing and Exploiting Leakage in VLSI Design by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri Boston, MA Springer US 2010 1 Online-Ressource txt rdacontent c rdamedia cr rdacarrier Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes) Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften Paul, Suganth Sonstige oth Garg, Rajesh Sonstige oth Gulati, Kanupriya Sonstige oth Khatri, Sunil P. Sonstige oth Erscheint auch als Druckausgabe 978-1-4419-0949-7 https://doi.org/10.1007/978-1-4419-0950-3 Verlag Volltext |
| spellingShingle | Jayakumar, Nikhil Minimizing and Exploiting Leakage in VLSI Design Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften |
| title | Minimizing and Exploiting Leakage in VLSI Design |
| title_auth | Minimizing and Exploiting Leakage in VLSI Design |
| title_exact_search | Minimizing and Exploiting Leakage in VLSI Design |
| title_full | Minimizing and Exploiting Leakage in VLSI Design by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri |
| title_fullStr | Minimizing and Exploiting Leakage in VLSI Design by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri |
| title_full_unstemmed | Minimizing and Exploiting Leakage in VLSI Design by Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri |
| title_short | Minimizing and Exploiting Leakage in VLSI Design |
| title_sort | minimizing and exploiting leakage in vlsi design |
| topic | Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften |
| topic_facet | Engineering Computer aided design Systems engineering Circuits and Systems Computer-Aided Engineering (CAD, CAE) and Design Ingenieurwissenschaften |
| url | https://doi.org/10.1007/978-1-4419-0950-3 |
| work_keys_str_mv | AT jayakumarnikhil minimizingandexploitingleakageinvlsidesign AT paulsuganth minimizingandexploitingleakageinvlsidesign AT gargrajesh minimizingandexploitingleakageinvlsidesign AT gulatikanupriya minimizingandexploitingleakageinvlsidesign AT khatrisunilp minimizingandexploitingleakageinvlsidesign |